On the design and implementation of a control system processor. - René Cumplido-Parra (2001)

A Hybrid Approach for Target Detection Using CFAR Algorithm and Image Processing. - Santos López-Estrada; René Cumplido-Parra; César Torres-Huitzil (ENC, 2004)

Design and Implementation of a CFAR Processor for Target Detection. - César Torres-Huitzil; René Cumplido-Parra; Santos López-Estrada (FPL, 2004)

High performance encryption cores for 3G networks. - Tomás Balderas-Contreras; René Cumplido (DAC, 2005)

Fusion center with neural network for target detection in background clutter. - Santos López-Estrada; René Cumplido-Parra (ENC, 2005)

On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004. - Joaquín García 003; René Cumplido-Parra (ReConFig, 2005)

An FPGA-based parallel sorting architecture for the Burrows Wheeler transform. - José Francisco Martínez Trinidad; René Cumplido-Parra; Claudia Feregrino Uribe (ReConFig, 2005)

A high-performance processor for embedded real-time control. - René Cumplido; Simon R. Jones; Roger Goodall; Stephen Bateman (IEEE Trans. Control. Syst. Technol., 2005)

On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification. - René Cumplido; Jesús Ariel Carrasco-Ochoa; Claudia Feregrino (CIARP, 2006)

Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. - Ignacio Algredo-Badillo; Claudia Feregrino Uribe; René Cumplido (ICCSA (3), 2006)

Decision Tree Based FPGA-Architecture for Texture Sea State Classification. - Santos López-Estrada; René Cumplido (ReConFig, 2006)

Parallel Hardware/Software Architecture for the BWT and LZ77 Lossless Data Compression Algorithms. - Virgilio Zúñiga Grajeda; Claudia Feregrino Uribe; René Cumplido-Parra (Computación y Sistemas, 2006)

FPGA-Based Architecture for Computing Testors. - Alejandro Rojas; René Cumplido; Jesús Ariel Carrasco-Ochoa; Claudia Feregrino Uribe; José Francisco Martínez Trinidad (IDEAL, 2007)

FPGA Hardware Architecture of the Steganographic ConText Technique. - Edgar Gomez-Hernández; Claudia Feregrino Uribe; René Cumplido (CONIELECOMP, 2008)

A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. - Roberto Perez-Andrade; René Cumplido; Claudia Feregrino Uribe; Fernando Martin del Campo (FPL, 2008)

A Versatile Linear Insertion Sorter Based on a FIFO Scheme. - Roberto Perez-Andrade; René Cumplido; Fernando Martin del Campo; Claudia Feregrino Uribe (ISVLSI, 2008)

FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. - Ignacio Algredo-Badillo; Claudia Feregrino Uribe; René Cumplido; Miguel Morales-Sandoval (ReConFig, 2008)

Hybrid Architecture for Data-Dependent Superimposed Training in Digital Receivers. - Fernando Martin del Campo; René Cumplido; Roberto Perez-Andrade; Aldo G. Orozco-Lugo (ReConFig, 2008)

FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems. - Jose Juan Garcia-Hernandez; Claudia Feregrino Uribe; René Cumplido (ReConFig, 2008)

A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation. - Zobeida Jezabel Guzman-Zavaleta; Claudia Feregrino Uribe; René Cumplido (ReConFig, 2008)

On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm. - Tomás Balderas-Contreras; René Cumplido; Claudia Feregrino Uribe (Comput. Electr. Eng., 2008)

Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description. - Ignacio Algredo-Badillo; Claudia Feregrino Uribe; René Cumplido; Miguel Morales-Sandoval (IEICE Trans. Inf. Syst., 2008)

Watermarking Based on Iterated Function Systems. - Pedro Aaron Hernandez-Avalos; Claudia Feregrino Uribe; Roger Luis Velázquez; René Cumplido-Parra (ENC, 2009)

A Run Time Reconfigurable Co-processor for Elliptic Curve Scalar Multiplication. - Miguel Morales-Sandoval; Claudia Feregrino Uribe; René Cumplido; Ignacio Algredo-Badillo (ENC, 2009)

FPGA-architecture for Knowledge-Based Target Detection in Radar Signal Processing. - Santos López-Estrada; René Cumplido (ERSA, 2009)

An area/performance trade-off analysis of a GF(2m) multiplier architecture for elliptic curve cryptography. - Miguel Morales-Sandoval; Claudia Feregrino Uribe; René Cumplido; Ignacio Algredo-Badillo (Comput. Electr. Eng., 2009)

Efficient implementation of the RDM-QIM algorithm in an FPGA. - Jose Juan Garcia-Hernandez; Carolina Reta; René Cumplido; Claudia Feregrino Uribe (IEICE Electron. Express, 2009)

A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation. - Fernando Martin del Campo; René Cumplido; Roberto Perez-Andrade; Aldo G. Orozco-Lugo (Int. J. Reconfigurable Comput., 2009)

A versatile linear insertion sorter based on an FIFO scheme. - Roberto Perez-Andrade; René Cumplido; Claudia Feregrino Uribe; Fernando Martin del Campo (Microelectron. J., 2009)

Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems. - René Cumplido; Juan M. Campos; Claudia Feregrino Uribe; Jose Roberto Perez-Andrade (Dynamically Reconfigurable Architectures, 2010)

A UML 2.0 Profile to Model Block Cipher Algorithms. - Tomás Balderas-Contreras; Gustavo Rodríguez Gómez; René Cumplido (ECMFA, 2010)

On the Design of a Hardware-Software Architecture for Acceleration of SVM's Training Phase. - Lázaro Bustio-Martínez; René Cumplido; José Hernández Palancar; Claudia Feregrino Uribe (MCPR, 2010)

A Highly Parallel Algorithm for Frequent Itemset Mining. - Alejandro Mesa; Claudia Feregrino Uribe; René Cumplido; José Hernández Palancar (MCPR, 2010)

Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard. - Ignacio Algredo-Badillo; Claudia Feregrino Uribe; René Cumplido; Miguel Morales-Sandoval (Comput. Electr. Eng., 2010)

A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter. - Roberto Perez-Andrade; René Cumplido; Claudia Feregrino Uribe; Fernando Martin del Campo (Digit. Signal Process., 2010)

Improving the security of Fallahpour's audio watermarking scheme. - Jose Juan Garcia-Hernandez; Claudia Feregrino Uribe; René Cumplido; Ramón Parra-Michel (IEICE Electron. Express, 2010)

Hardware architecture for adaptive filtering based on energy-CFAR processor for radar target detection. - Santos López-Estrada; René Cumplido (IEICE Electron. Express, 2010)

A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation. - Miguel Morales-Sandoval; Claudia Feregrino Uribe; René Cumplido; Ignacio Algredo-Badillo (J. Circuits Syst. Comput., 2010)

Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. - Ignacio Algredo-Badillo; Claudia Feregrino Uribe; René Cumplido; Miguel Morales-Sandoval (DSD, 2011)

RAW Introduction. - Jürgen Becker 001; Pascal Benoit; René Cumplido (IPDPS Workshops, 2011)

On a Hybrid and General Control Scheme for Algorithms Represented as a Polytope. - Roberto Perez-Andrade; César Torres-Huitzil; René Cumplido; Juan M. Campos (IPDPS Workshops, 2011)

Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware - Experiences on teaching and research. - René Cumplido; Claudia Feregrino Uribe; Jose Juan Garcia-Hernandez (ReCoSoC, 2011)

On the Implementation of a Hardware Architecture for an Audio Data Hiding System. - Jose Juan Garcia-Hernandez; Claudia Feregrino Uribe; René Cumplido; Carolina Reta (J. Signal Process. Syst., 2011)

RAW Introduction. - Jürgen Becker 001; Jinian Bian; Christophe Bobda; René Cumplido; Michael Hübner 001 (IPDPS Workshops, 2012)

Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm. - Ignacio Algredo-Badillo; Miguel Morales-Sandoval; Claudia Feregrino Uribe; René Cumplido (ISVLSI, 2012)

Watermarking using similarities based on fractal codification. - Pedro Aaron Hernandez-Avalos; Claudia Feregrino Uribe; René Cumplido (Digit. Signal Process., 2012)

Hardware-software platform for computing irreducible testors. - Alejandro Rojas; René Cumplido; Jesús Ariel Carrasco-Ochoa; Claudia Feregrino; José Francisco Martínez Trinidad (Expert Syst. Appl., 2012)

A multi-cycle fixed point square root module for FPGAs. - Fernando Martin del Campo; Alicia Morales-Reyes; Roberto Perez-Andrade; René Cumplido; Aldo G. Orozco-Lugo; Claudia Feregrino (IEICE Electron. Express, 2012)

High Throughput Signature Based Platform for Network Intrusion Detection. - José Manuel Bande Serrano; José Hernández Palancar; René Cumplido (CIARP (2), 2013)

RAW Introduction. - Jürgen Becker 001; Ramachandran Vaidyanathan; Peter Athanas; Marco D. Santambrogio; René Cumplido; Oliver Sander (IPDPS Workshops, 2013)

Video Error Concealment Based on Data Hiding for the Emerging Video Technologies. - Francisco Aguirre-Ramos; Claudia Feregrino Uribe; René Cumplido (PSIVT, 2013)

Processor arrays generation for matrix algorithms used in embedded platforms. - Roberto Perez-Andrade; César Torres-Huitzil; René Cumplido; Juan M. Campos (ReConFig, 2013)

A parallelization methodology for reconfigurable systems applied to edge detection. - Juan M. Campos; René Cumplido; Claudia Feregrino Uribe; Roberto Perez-Andrade (ReCoSoC, 2013)

A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m. - Eduardo Cuevas-Farfan; Miguel Morales-Sandoval; René Cumplido; Claudia Feregrino Uribe; Ignacio Algredo-Badillo (ReCoSoC, 2013)

Area/performance trade-off analysis of an FPGA digit-serial GF(2m)GF(2m) Montgomery multiplier based on LFSR. - Miguel Morales-Sandoval; Claudia Feregrino Uribe; Paraskevas Kitsos; René Cumplido (Comput. Electr. Eng., 2013)

High payload data-hiding in audio signals based on a modified OFDM approach. - Jose Juan Garcia-Hernandez; Ramón Parra-Michel; Claudia Feregrino Uribe; René Cumplido (Expert Syst. Appl., 2013)

On an external memory scheme for processor arrays. - Roberto Perez-Andrade; César Torres-Huitzil; René Cumplido; Juan M. Campos (IEICE Electron. Express, 2013)

Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011). - René Cumplido; Peter Athanas; Jürgen Becker 001 (Int. J. Reconfigurable Comput., 2013)

FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256. - Ignacio Algredo-Badillo; Claudia Feregrino Uribe; René Cumplido; Miguel Morales-Sandoval (Microprocess. Microsystems, 2013)

Multi-character cost-effective and high throughput architecture for content scanning. - José Manuel Bande Serrano; José Hernández Palancar; René Cumplido (Microprocess. Microsystems, 2013)

Introduction to the special section on 19th reconfigurable architectures workshop (RAW 2012). - Diana Goehringer; René Cumplido (ACM Trans. Reconfigurable Technol. Syst., 2013)

The Evaluation of Ordered Features for SMS Spam Filtering. - José Manuel Bande Serrano; José Hernández Palancar; René Cumplido (CIARP, 2014)

FSM merging and reduction for IP cores watermarking using Genetic Algorithms. - Jorge Echavarria; Alicia Morales-Reyes; René Cumplido; Miguel A. Salido (ReConFig, 2014)

A hardware architecture for filtering irreducible testors. - Vladimir Rodriguez; José F. Martínez; Jesús Ariel Carrasco-Ochoa; Manuel Sabino Lazo-Cortés; René Cumplido; Claudia Feregrino Uribe (ReConFig, 2014)

Introduction to the special issue on FPGA Technology and Applications. - Peter Athanas; René Cumplido; Eduardo de la Torre (Comput. Electr. Eng., 2014)

A compact FPGA-based processor for the Secure Hash Algorithm SHA-256. - Rommel García; Ignacio Algredo-Badillo; Miguel Morales-Sandoval; Claudia Feregrino Uribe; René Cumplido (Comput. Electr. Eng., 2014)

Hardware architecture for security improved Fallahpour audio watermarking scheme. - Claudia Feregrino Uribe; Ernesto Aparicio-Díaz; José Juan García-Hernández; Alejandra Menendez-Ortiz; René Cumplido; Alicia Morales-Reyes (IEICE Electron. Express, 2014)

Synthesizing VHDL from Activity Models in UML 2. - Tomás Balderas-Contreras; René Cumplido; Gustavo Rodríguez Gómez (Int. J. Circuit Theory Appl., 2014)

Introduction to Special issue on FPGA Devices and Applications. - Peter M. Athanas; René Cumplido; Claudia Feregrino Uribe; Eduardo de la Torre (Microprocess. Microsystems, 2014)

Hardware Acceleration of Frequent Itemsets Mining on Data Streams. - Lázaro Bustio-Martínez; René Cumplido-Parra; Raudel Hernández-León; Claudia Feregrino Uribe (Res. Comput. Sci., 2014)

An Empirical Analysis on Dimensionality in Cellular Genetic Algorithms. - Alicia Morales-Reyes; Hugo Jair Escalante; Martín Letras; René Cumplido (GECCO, 2015)

Frequent Itemsets Mining in Data Streams Using Reconfigurable Hardware. - Lázaro Bustio; René Cumplido; Raudel Hernández-León; José Manuel Bande Serrano; Claudia Feregrino (NFMCP, 2015)

Message from chairs. - Maya B. Gokhale; Michael Hübner 001; René Cumplido (ReConFig, 2015)

Accelerating the construction of BRIEF descriptors using an FPGA-based architecture. - Roberto de Lima; José Martínez-Carranza; Alicia Morales-Reyes; René Cumplido (ReConFig, 2015)

An analysis of computational models for accelerating the subtractive pixel adjacency model computation. - Marisol Rodriguez-Perez; Alicia Morales-Reyes; René Cumplido; Claudia Feregrino Uribe (Comput. Electr. Eng., 2015)

A fast hardware software platform for computing irreducible testors. - Vladimir Rodríguez-Diez; José Francisco Martínez Trinidad; Jesús Ariel Carrasco-Ochoa; Manuel Lazo-Cortés; Claudia Feregrino Uribe; René Cumplido (Expert Syst. Appl., 2015)

Introduction to Special issue on Reconfigurable computing and FPGAs. - René Cumplido; Eduardo de la Torre; Claudia Feregrino Uribe; Michael J. Wirthlin (Microprocess. Microsystems, 2015)

Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs. - Roberto Perez-Andrade; César Torres-Huitzil; René Cumplido (Microprocess. Microsystems, 2015)

Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning. - Martín Letras; Raudel Hernández-León; René Cumplido (IPDPS Workshops, 2016)

An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using a Linear Sorter. - Juan Andrés Pérez-Celis; José Martínez-Carranza; Alicia Morales-Reyes; Claudia Feregrino Uribe; René Cumplido (IPDPS Workshops, 2016)

Introduction to the Special Section on FPGAs Technology and Applications. - René Cumplido; Peter Athanas; Eduardo de la Torre (Comput. Electr. Eng., 2016)

Introduction to the special section on FPGAs Technology and Applications. - René Cumplido; Michael Hübner 001; Michael J. Wirthlin (Comput. Electr. Eng., 2016)

A scalable and customizable processor array for implementing cellular genetic algorithms. - Martín Letras; Alicia Morales-Reyes; René Cumplido (Neurocomputing, 2016)

Approximate frequent itemsets mining on data streams using hashing and lexicographie order in hardware. - Lázaro Bustio-Martínez; René Cumplido; Mauro Martín Letras Luna; Claudia Feregrino Uribe; Raudel Hernández-León; José Manuel Bande Serrano (LASCAS, 2017)

A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption. - Luis Armando Rodriguez Flores; Miguel Morales-Sandoval; René Cumplido; Claudia Feregrino Uribe; Ignacio Algredo-Badillo (LASCAS, 2017)

Improving the construction of ORB through FPGA-based acceleration. - Roberto de Lima; José Martínez-Carranza; Alicia Morales-Reyes; René Cumplido (Mach. Vis. Appl., 2017)

An FPGA-based programmable processor for bilinear pairings. - Eduardo Cuevas-Farfan; Miguel Morales-Sandoval; René Cumplido (IACR Cryptol. ePrint Arch., 2018)

On the design of hardware-software architectures for frequent itemsets mining on data streams. - Lázaro Bustio-Martínez; René Cumplido; Raudel Hernández-León; José Manuel Bande Serrano; Claudia Feregrino Uribe (J. Intell. Inf. Syst., 2018)

Detection And Localization Of Splicing Attacks On Videos Using Block Correlation. - Ernesto Aparicio-Díaz; René Cumplido; Lázaro Bustio-Martínez; Claudia Feregrino Uribe (PACRIM, 2019)

Temporal Copy-Move Forgery Detection and Localization Using Block Correlation Matrix. - Ernesto Aparicio-Díaz; René Cumplido; Maikel L. Pérez Gort; Claudia Feregrino Uribe (J. Intell. Fuzzy Syst., 2019)

Using hashing and lexicographic order for Frequent Itemsets Mining on data streams. - Lázaro Bustio-Martínez; Mauro Martín Letras Luna; René Cumplido; Raudel Hernández-León; Claudia Feregrino Uribe; José Manuel Bande Serrano (J. Parallel Distributed Comput., 2019)

Guest Editorial: Special Issue on Reconfigurable Computing and FPGA Technology. - René Cumplido; Maya B. Gokhale; Claudia Feregrino; Michael Hübner 001 (J. Parallel Distributed Comput., 2019)

A novel multi-core algorithm for frequent itemsets mining in data streams. - Lázaro Bustio-Martínez; Alfredo Muñoz-Briseño; René Cumplido; Raudel Hernández-León; Claudia Feregrino Uribe (Pattern Recognit. Lett., 2019)

On the design of hardware architectures for parallel frequent itemsets mining. - Martín Letras; Lázaro Bustio-Martínez; René Cumplido; Raudel Hernández-León; Claudia Feregrino Uribe (Expert Syst. Appl., 2020)

IP-cores watermarking scheme at behavioral level using genetic algorithms. - Jorge Echavarria; Alicia Morales-Reyes; René Cumplido; Miguel A. Salido; Claudia Feregrino Uribe (Eng. Appl. Artif. Intell., 2021)

A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks. - Miguel Morales-Sandoval; Luis Armando Rodriguez Flores; René Cumplido; Jose Juan Garcia-Hernandez; Claudia Feregrino; Ignacio Algredo-Badillo (J. Sensors, 2021)

Reversible Image Authentication Scheme with Tampering Reconstruction Based on Very Deep Super Resolution Network. - G. Melendez-Melendez; René Cumplido (MICAI (1), 2022)

FPGA/GPU-based Acceleration for Frequent Itemsets Mining: A Comprehensive Review. - Lázaro Bustio-Martínez; René Cumplido; Martín Letras; Raudel Hernández-León; Claudia Feregrino Uribe; José Hernández Palancar (ACM Comput. Surv., 2022)

A lightweight data representation for phishing URLs detection in IoT environments. - Lázaro Bustio-Martínez; Miguel Ángel Álvarez-Carmona; Vitali Herrera-Semenets; Claudia Feregrino Uribe; René Cumplido (Inf. Sci., 2022)

An adaptive method for prevention of overflow in reversible data hiding schemes. - Alejandro Peñuelas-Angulo; Claudia Feregrino Uribe; René Cumplido (Expert Syst. Appl., 2023)

A secure DWT-based dual watermarking scheme for image authentication and copyright protection. - A. Hernández-Joaquín; G. Melendez-Melendez; René Cumplido (Multim. Tools Appl., 2023)

An adaptive pixel value ordering based reversible data hiding scheme for images. - G. Melendez-Melendez; Alicia Morales-Reyes; René Cumplido (Expert Syst. Appl., 2023)

A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms. - Martín Letras; Alicia Morales-Reyes; René Cumplido; María-Guadalupe Martínez-Peñaloza; Claudia Feregrino Uribe (Microprocess. Microsystems, 2024)

Design and Implementation of Hardware-Software Architecture Based on Hashes for SPHINCS+. - Jonathan Lopez-Valdivieso; René Cumplido (ACM Trans. Reconfigurable Technol. Syst., 2024)

Adaptive Intrusion Detection System: Hybrid K-Means and Random Forest Approach with Concept Drift Detection. - Eric Garcia-Huitzitl; Lázaro Bustio-Martínez; René Cumplido (Computación y Sistemas (CyS), 2025)