A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features. - René Kothe; Christian Galke; Heinrich Theodor Vierhaus (IOLTS, 2005)

Logic Self Repair. - Christian Galke; René Kothe; Heinrich Theodor Vierhaus (ARCS Workshops, 2006)

Hardware/Software Based Hierarchical Self Test for SoCs. - René Kothe; Christian Galke; Sabine Schultke; Henry Fröschke; Steffen Gaede; Heinrich Theodor Vierhaus (DDECS, 2006)

Embedded Self Repair by Transistor and Gate Level Reconfiguration. - René Kothe; Heinrich Theodor Vierhaus; Torsten Coym; Wolfgang Vermeiren; Bernd Straube (DDECS, 2006)

Embedded Scan Test with Diagnostic Features for Self-Testing SoCs. - Christian Galke; René Kothe; Sabine Schultke; K. Winkler; Jeanette Honko; Heinrich Theodor Vierhaus (IOLTS, 2006)

Built-in Self Repair by Reconfiguration of FPGAs. - S. Habermann; René Kothe; Heinrich Theodor Vierhaus (IOLTS, 2006)

Flip-Flops and Scan-Path Elements for Nanoelectronics. - René Kothe; Heinrich Theodor Vierhaus (DDECS, 2007)

A Configurable Modular Test Processor and Scan Controller Architecture. - R. Frost; D. Rudolph; Christian Galke; René Kothe; Heinrich Theodor Vierhaus (IOLTS, 2007)

Embedded Diagnostic Logic Test Exploiting Regularity. - Heinrich Theodor Vierhaus; René Kothe (DSD, 2008)

A Scan Controller Concept for Low Power Scan Tests. - René Kothe; Heinrich Theodor Vierhaus (J. Low Power Electron., 2008)

Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures. - René Kothe; Heinrich Theodor Vierhaus (DSD, 2010)