Untersuchungen zur Gunn-Elektronik unter besonderer Berücksichtigung der numerischen Analyse. - Rainer Götze 002; René Schüffny (1977)

An Architectural Study of a Massively Parallel Processor for Convolution-Type Operations in Complex Vision Tasks. - Martin Franz; René Schüffny (ICANN, 1996)

A VLSI chip for wavelet image compression. - M. Schwarzenberg; M. Traber; M. Scholles; René Schüffny (ISCAS (4), 1999)

Design of parallel preprocessing image sensors. - Jörg Schreiter; Rico Srowik; Achim Graupner; Stefan Getzlaff; René Schüffny (KES, 1999)

Robust Implementation and Statistical Modeling of a VI-Converter. - Achim Graupner; René Schüffny (SBCCI, 2000)

A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing. - Stefan Getzlaff; Jörg Schreiter; Achim Graupner; René Schüffny (ISCAS (4), 2001)

Minimizing charge injection errors in high-precision, high-speed SC-circuits. - Jörg Krupar; Rico Srowik; Jörg Schreiter; Achim Graupner; René Schüffny; Udo Jörges (ISCAS (1), 2001)

A vision device for image processing. - Achim Graupner; Stefan Getzlaff; Jörg Schreiter; René Schüffny (SIP, 2001)

CMOS image sensor with shared in-pixel amplifier and calibration facility. - Achim Graupner; M. Tanzer; René Schüffny (APCCAS (2), 2002)

An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights. - Arne Heittmann; Ulrich Ramacher; Daniel Matolin; Jörg Schreiter; René Schüffny (ICANN, 2002)

Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity. - Jörg Schreiter; Ulrich Ramacher; Arne Heittmann; D. Matolini; René Schüffny (NNSP, 2002)

Segmentation of Blood Vessels in Subtraction Angiographic Images. - Martin Franz; René Schüffny (DICTA, 2003)

Concept of Color Correction on Multi-Channel CMOS Sensors. - Stephan Henker; Jens-Uwe Schluessler; René Schüffny (DICTA, 2003)

High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications. - Riad Stefo; Jörg Schreiter; Jens-Uwe Schluessler; René Schüffny (FPT, 2003)

Comparison of accumulation units for analog realizations of a path searcher for a UMTS receiver. - Achim Graupner; Sven Linzmajer; Gerhard P. Fettweis; René Schüffny (ICECS, 2003)

Optimized filter banks for the compression of subtraction angiographic images. - Martin Franz; René Schüffny (ISSPA (1), 2003)

On-chip digital noise reduction for integrated CMOS Cameras. - Markus Rullmann; Jens-Uwe Schluessler; René Schüffny (VCIP, 2003)

CMOS image sensor with mixed-signal processor array. - Achim Graupner; Jörg Schreiter; Stefan Getzlaff; René Schüffny (IEEE J. Solid State Circuits, 2003)

Pulse coupled neural networks with adaptive synapses for image segmentation. - Jörg Schreiter; Ulrich Ramacher; Arne Heittmann; Daniel Matolin; René Schüffny (ARCS Workshops, 2004)

Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation. - Jörg Schreiter; Ulrich Ramacher; Arne Heittmann; Daniel Matolin; René Schüffny (Image Processing: Algorithms and Systems, 2004)

An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation. - Daniel Matolin; Jörg Schreiter; Stefan Getzlaff; René Schüffny (PARELEC, 2004)

Design and evaluation of current-mode image sensors in CMOS-technology. - Matthias Tänzer; Achim Graupner; René Schüffny (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

Applying Spiking Neural Nets to Noise Shaping. - Christian Mayr 001; René Schüffny (IEICE Trans. Inf. Syst., 2005)

Neighborhood Rank Order Coding for Robust Texture Analysis and Feature Extraction. - Christian Mayr 001; René Schüffny (HIS, 2007)

Gabor-Like Image Filtering Using a Neural Microcircuit. - Christian Mayr 001; Arne Heittmann; René Schüffny (IEEE Trans. Neural Networks, 2007)

BCM and Membrane Potential: Alternative Ways to Timing Dependent Plasticity. - Johannes Partzsch; Christian Mayr 001; René Schüffny (ICONIP (1), 2008)

On the routing complexity of neural network models - Rent's Rule revisited. - Johannes Partzsch; René Schüffny (ESANN, 2009)

Current conveyor based amplifier and adaptive buffer for use in an analog frontend. - Georg Ellguth; Stephan Henker; Christian Mayr 001; René Schüffny (ICECS, 2009)

A low-power continuous-time incremental 2nd-order-MASH ΣΔ-modulator for a CMOS imager. - Johannes Uhlig; René Schüffny; Harald Neubauer; Johann Hauer; Joachim Haase (ICECS, 2009)

On the Relation between Bursts and Dynamic Synapse Properties: A Modulation-Based Ansatz. - Christian Mayr 001; Johannes Partzsch; René Schüffny (Comput. Intell. Neurosci., 2009)

Transient responses of activity-dependent synapses to modulated pulse trains. - Christian Mayr 001; Johannes Partzsch; René Schüffny (Neurocomputing, 2009)

A novel ADPLL design using successive approximation frequency control. - Holger Eisenreich; Christian Mayr 001; Stephan Henker; Michael Wickert; René Schüffny (Microelectron. J., 2009)

A Software Framework for Mapping Neural Networks to a Wafer-scale Neuromorphic Hardware System. - Matthias Ehrlich; Karsten Wendt; Lukas Zühl; René Schüffny; Daniel Brüderle; Eric Müller 001; Bernhard Vogginger (ANNIIP, 2010)

GMPath - A Path Language for Navigation, Information Query and Modification of Data Graphs. - Karsten Wendt; Matthias Ehrlich; René Schüffny (ANNIIP, 2010)

A critique of BCM behavior verification for STDP-type plasticity models. - Christian Mayr 001; Johannes Partzsch; René Schüffny (ESANN, 2010)

Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput. - Stephan Hartmann 002; Stefan Schiefer; Stefan Scholze; Johannes Partzsch; Christian Mayr 001; Stephan Henker; René Schüffny (ICECS, 2010)

Wide swing signal amplification by SC voltage doubling. - Sebastian Höppner; René Schüffny; Zuo-Min Tsai; Huei Wang (ISCAS, 2010)

Replicating experimental spike and rate based neural learning in CMOS. - Christian Mayr 001; Marko Noack; Johannes Partzsch; René Schüffny (ISCAS, 2010)

A low-power cell-based-design multi-port register file in 65nm CMOS technology. - Johannes Uhlig; Sebastian Höppner; Georg Ellguth; René Schüffny (ISCAS, 2010)

Efficient compensation of delay variations in high-speed network-on-chip data links. - Sebastian Höppner; Dennis Walter; Holger Eisenreich; René Schüffny (SoC, 2010)

Synapse dynamics in CMOS derived from a model of neurotransmitter release. - Marko Noack; Christian Mayr 001; Johannes Partzsch; René Schüffny (ECCTD, 2011)

Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput. - Stefan Schiefer; Stephan Hartmann 002; Stefan Scholze; Johannes Partzsch; Christian Mayr 001; Stephan Henker; René Schüffny (ISCAS, 2011)

Mismatch characterization of high-speed NoC links using asynchronous sub-sampling. - Sebastian Höppner; Dennis Walter; Georg Ellguth; René Schüffny (SoC, 2011)

An empirical study of the stability of 4th-order Incremental-ΣΔ-ADCs. - Johannes Uhlig; René Schüffny (NORCHIP, 2011)

A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems. - Daniel Brüderle; Mihai A. Petrovici; Bernhard Vogginger; Matthias Ehrlich; Thomas Pfeil; Sebastian Millner; Andreas Grübl; Karsten Wendt; Eric Müller 001; Marc-Olivier Schwartz; Dan Husmann de Oliveira; Sebastian Jeltsch; et al. (Biol. Cybern., 2011)

Analyzing the Scaling of Connectivity in Neuromorphic Hardware and in Models of Neural Networks. - Johannes Partzsch; René Schüffny (IEEE Trans. Neural Networks, 2011)

Dedicated FPGA communication architecture and design for a large-scale neuromorphic system. - Vasilis N. Thanasoulis; Johannes Partzsch; Stephan Hartmann 002; Christian Mayr 001; René Schüffny (ICECS, 2012)

Long-term pulse stimulation and recording in an accelerated neuromorphic system. - Vasilis N. Thanasoulis; Johannes Partzsch; Bernhard Vogginger; Christian Mayr 001; René Schüffny (ICECS, 2012)

Incremental-ΣΔ-ADCs with dynamic conversion length adaption. - Johannes Uhlig; René Schüffny (ICECS, 2012)

A 14 bit self-calibrating charge redistribution SAR ADC. - Stefan Hänzsche; Stephan Henker; René Schüffny; Thomas Reichel; Matthias Garzarolli (ISCAS, 2012)

A power management architecture for fast per-core DVFS in heterogeneous MPSoCs. - Sebastian Höppner; Chenming Shao; Holger Eisenreich; Georg Ellguth; Mario Ander; René Schüffny (ISCAS, 2012)

Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system. - Johannes Schemmel; Andreas Grübl; Stephan Hartmann 002; Alexander Kononov; Christian Mayr 001; Karlheinz Meier; Sebastian Millner; Johannes Partzsch; Stefan Schiefer; Stefan Scholze; René Schüffny; Marc-Olivier Schwartz (ISCAS, 2012)

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS. - Dennis Walter; Sebastian Höppner; Holger Eisenreich; Georg Ellguth; Stephan Henker; Stefan Hänzsche; René Schüffny; Markus Winter 002; Gerhard P. Fettweis (ISSCC, 2012)

A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates. - Markus Winter 002; Steffen Kunze; Esther P. Adeva; Björn Mennenga; Emil Matús; Gerhard P. Fettweis; Holger Eisenreich; Georg Ellguth; Sebastian Höppner; Stefan Scholze; René Schüffny; Tomoyoshi Kobori (ISSCC, 2012)

Waveform Driven Plasticity in BiFeO3 Memristive Devices: Model and Implementation. - Christian Mayr 001; Paul Stärke; Johannes Partzsch; René Schüffny; Love Cederstroem; Yao Shuai; Nan Du 004; Heidemarie Schmidt (NIPS, 2012)

Developing structural constraints on connectivity for biologically embedded neural networks. - Johannes Partzsch; René Schüffny (Biol. Cybern., 2012)

On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links. - Sebastian Höppner; Dennis Walter; Georg Ellguth; René Schüffny (Int. J. Embed. Real Time Commun. Syst., 2012)

A 32 GBit/s communication SoC for a waferscale neuromorphic system. - Stefan Scholze; Holger Eisenreich; Sebastian Höppner; Georg Ellguth; Stephan Henker; Mario Ander; Stefan Hänzsche; Johannes Partzsch; Christian Mayr 001; René Schüffny (Integr., 2012)

Accuracy evaluation of numerical methods used in state-of-the-art simulators for spiking neural networks. - Stephan Henker; Johannes Partzsch; René Schüffny (J. Comput. Neurosci., 2012)

Behavioral model of a continuous current integrator with time discrete feedback and sampling. - Johannes Gorner; Johannes Uhlig; Stefan Hänzsche; René Schüffny (ECCTD, 2013)

Analysis of a charge redistribution SAR ADC with partially thermometer coded DAC. - Stefan Hänzsche; René Schüffny (ECCTD, 2013)

Live demonstration: A 90GBit/s serial NoC link over 6mm in 65nm CMOS technology. - Sebastian Höppner; Dennis Walter; Holger Eisenreich; Stefan Schiefer; René Schüffny (ECCTD, 2013)

Live demonstration: Ethernet communication linking two large-scale neuromorphic systems. - Johannes Partzsch; Christian Mayr 001; Bernhard Vogginger; René Schüffny; Alexander D. Rast; Luis A. Plana; Steve B. Furber (ECCTD, 2013)

Rapid prototyping of higher order incremental ΣΔ-ADC topologies and NTFs. - Johannes Uhlig; Stefan Hänzsche; René Schüffny; Thomas Reichel; Lars Gopfert; Valeri Razhenikov (ICECS, 2013)

A location-independent direct link neuromorphic interface. - Alexander D. Rast; Johannes Partzsch; Christian Mayr 001; Johannes Schemmel; Stefan Hartmann; Luis A. Plana; Steve Temple; David R. Lester; René Schüffny; Steve B. Furber (IJCNN, 2013)

A model based comparison of BiFeO3 device applicability in neuromorphic hardware. - Love Cederstroem; Paul Stärke; Christian Mayr 001; Yao Shuai; Heidemarie Schmidt; René Schüffny (ISCAS, 2013)

Live demonstration: Multiple-timescale plasticity in a neuromorphic system. - Christian Mayr 001; Johannes Partzsch; Marko Noack; René Schüffny (ISCAS, 2013)

Hybrid incremental-ΣΔ-ADC for ambient light sensing applications. - Johannes Uhlig; Stefan Hänzsche; Johannes Gorner; René Schüffny; Thomas Reichel; Lars Gopfert (ISCAS, 2013)

Neural Schematics as a unified formal graphical representation of large-scale Neural Network Structures. - Matthias Ehrlich; René Schüffny (Frontiers Neuroinformatics, 2013)

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology. - Sebastian Höppner; Stefan Hänzsche; Georg Ellguth; Dennis Walter; Holger Eisenreich; René Schüffny (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology. - Sebastian Höppner; Holger Eisenreich; Stephan Henker; Dennis Walter; Georg Ellguth; René Schüffny (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Integrated circuits processing chemical information: Prospects and challenges. - Andreas Richter 002; Andreas Voigt; René Schüffny; Stephan Henker; Marcus Völp (DATE, 2014)

An energy efficient multi-bit TSV transmitter using capacitive coupling. - Johannes Gorner; Sebastian Höppner; Dennis Walter; Michael Haas; Dirk Plettemeier; René Schüffny (ICECS, 2014)

Configurable pulse routing architecture for accelerated multi-node neuromorphic systems. - Vasilis N. Thanasoulis; Johannes Partzsch; Bernhard Vogginger; René Schüffny (ICECS, 2014)

A compact on-chip IR-drop measurement system in 28 nm CMOS technology. - Sebastian Dietel; Sebastian Höppner; Holger Eisenreich; Georg Ellguth; Stefan Hänzsche; Stephan Henker; René Schüffny; Tim Brauninger; Ulrich Fiedler (ISCAS, 2014)

VLSI implementation of a conductance-based multi-synapse using switched-capacitor circuits. - Marko Noack; Markus Krause; Christian Mayr 001; Johannes Partzsch; René Schüffny (ISCAS, 2014)

A pulse communication flow ready for accelerated neuromorphic experiments. - Vasilis N. Thanasoulis; Bernhard Vogginger; Johannes Partzsch; René Schüffny (ISCAS, 2014)

10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS. - Benedikt Noethen; Oliver Arnold; Esther P. Adeva; Tobias Seifert; Erik Fischer; Steffen Kunze; Emil Matús; Gerhard P. Fettweis; Holger Eisenreich; Georg Ellguth; Stephan Hartmann 002; Sebastian Höppner; et al. (ISSCC, 2014)

A 10 bit 16 MS/s redundant SAR ADC with flexible window function for a digitally controlled DC-DC converter in 28 nm CMOS. - Stefan Hänzsche; Sebastian Höppner; René Schüffny (NORCHIP, 2014)

OTA based 200 GΩ resistance on 700 μm2 in 180 nm CMOS for neuromorphic applications. - Christian Mayr 001; Michael Schultz; Marko Noack; Stephan Henker; Johannes Partzsch; René Schüffny (CoRR, 2014)

Switched-Capacitor Realization of Presynaptic Short-Term-Plasticity and Stop-Learning Synapses in 28 nm CMOS. - Marko Noack; Johannes Partzsch; Christian Mayr 001; Stefan Hänzsche; Stefan Scholze; Sebastian Höppner; Georg Ellguth; René Schüffny (CoRR, 2014)

Bridging the gap between software simulation and emulation on neuromorphic hardware: An investigation of causes, effects and compensation of network-level anomalies in a mixed-signal waferscale neuromorphic modeling platform. - Mihai A. Petrovici; Bernhard Vogginger; Paul Müller 002; Oliver Breitwieser; Mikael Lundqvist; Lyle Muller; Matthias Ehrlich; Alain Destexhe; Anders Lansner; René Schüffny; Johannes Schemmel; Karlheinz Meier (CoRR, 2014)

A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology. - Stefan Hänzsche; Sebastian Höppner; Georg Ellguth; René Schüffny (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An all-digital PWM generator with 62.5ps resolution in 28nm CMOS technology. - Sebastian Höppner; Stefan Hänzsche; Stefan Scholze; René Schüffny (ISCAS, 2015)

A deep-submicron CMOS flow for general-purpose timing-detection insertion. - Andreas Dixius; Dennis Walter; Sebastian Höppner; Holger Eisenreich; René Schüffny (MIXDES, 2015)

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS. - Sebastian Höppner; Dennis Walter; Thomas Hocker; Stephan Henker; Stefan Hänzsche; Daniel Sausner; Georg Ellguth; Jens-Uwe Schluessler; Holger Eisenreich; René Schüffny (IEEE J. Solid State Circuits, 2015)

An MPSoC for energy-efficient database query processing. - Sebastian Haas; Oliver Arnold; Benedikt Nöthen; Stefan Scholze; Georg Ellguth; Andreas Dixius; Sebastian Höppner; Stefan Schiefer; Stephan Hartmann 002; Stephan Henker; Thomas Hocker; Jörg Schreiter; et al. (DAC, 2016)

A database accelerator for energy-efficient query processing and optimization. - Sebastian Haas; Oliver Arnold; Stefan Scholze; Sebastian Höppner; Georg Ellguth; Andreas Dixius; Annett Ungethüm; Eric Mier; Benedikt Noethen; Emil Matús; Stefan Schiefer; Love Cederstroem; et al. (NORCAS, 2016)

A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits. - Christian Mayr 001; Johannes Partzsch; Marko Noack; Stefan Hänzsche; Stefan Scholze; Sebastian Höppner; Georg Ellguth; René Schüffny (IEEE Trans. Biomed. Circuits Syst., 2016)

A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring. - Sebastian Höppner; Johannes Partzsch; Johannes Neumann; René Schüffny; Christian Mayr 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications. - Sebastian Haas; Tobias Seifert; Benedikt Nöthen; Stefan Scholze; Sebastian Höppner; Andreas Dixius; Esther Pérez Adeva; Thomas R. Augustin; Friedrich Pauls; Sadia Moriam; Mattis Hasler; Erik Fischer; et al. (DAC, 2017)

Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system. - Sebastian Schmitt; Johann Klähn; Guillaume Bellec; Andreas Grübl; Maurice Güttler; Andreas Hartel; Stephan Hartmann 002; Dan Husmann de Oliveira; Kai Husmann; Sebastian Jeltsch; Vitali Karasenko; Mitja Kleider; et al. (IJCNN, 2017)

A fixed point exponential function accelerator for a neuromorphic many-core system. - Johannes Partzsch; Sebastian Höppner; Matthias Eberlein; René Schüffny; Christian Mayr 001; David R. Lester; Steve B. Furber (ISCAS, 2017)

Pattern representation and recognition with accelerated analog neuromorphic systems. - Mihai A. Petrovici; Sebastian Schmitt; Johann Klähn; Robert D. St. Louis; Anna Schroeder; Guillaume Bellec; Johannes Bill; Oliver Breitwieser; Ilja Bytschok; Andreas Grübl; Maurice Güttler; Andreas Hartel; et al. (ISCAS, 2017)

Pattern representation and recognition with accelerated analog neuromorphic systems. - Mihai A. Petrovici; Sebastian Schmitt; Johann Klähn; David Stöckel; Anna Schroeder; Guillaume Bellec; Johannes Bill; Oliver Breitwieser; Ilja Bytschok; Andreas Grübl; Maurice Güttler; Andreas Hartel; et al. (CoRR, 2017)

Application-specific architectures for energy-efficient database query processing and optimization. - Sebastian Haas; Stefan Scholze; Sebastian Höppner; Annett Ungethüm; Christian Mayr 001; René Schüffny; Wolfgang Lehner; Gerhard P. Fettweis (Microprocess. Microsystems, 2017)

Mean Field Approach for Configuring Population Dynamics on a Biohybrid Neuromorphic System. - Johannes Partzsch; Christian Mayr 001; Massimiliano Giulioni; Marko Noack; Stefan Hänzsche; Stefan Scholze; Sebastian Höppner; Paolo Del Giudice; René Schüffny (J. Signal Process. Syst., 2020)