René van Leuken

According to our database1, René van Leuken authored at least 56 papers between 1993 and 2019.

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Bibliography

2019
Towards Robust Inference of Biomedical Signals in Energy-Efficient Neuromorphic Networks.
Proceedings of the IEEE 1st Global Conference on Life Sciences and Technologies, 2019

Heterogeneous Activation Function Extraction for Training and Optimization of SNN Systems.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

Towards Computationally-Efficient Cognitive Sensor Systems for Autonomous Vehicles.
Proceedings of the 18th IEEE International Conference on Cognitive Informatics & Cognitive Computing, 2019

2018
A Real-Time Reconfigurable Multichip Architecture for Large-Scale Biophysically Accurate Neuron Simulation.
IEEE Trans. Biomed. Circuits Syst., 2018

Uncertainty in Noise-Driven Steady-State Neuromorphic Network for ECG Data Classification.
Proceedings of the 31st IEEE International Symposium on Computer-Based Medical Systems, 2018

Energy-efficient multipath ring network for heterogeneous clustered neuronal arrays.
Proceedings of the 2018 IEEE EMBS International Conference on Biomedical & Health Informatics, 2018

2017
Fighting Dark Silicon: Toward Realizing Efficient Thermal-Aware 3-D Stacked Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Immediate Neighborhood Temperature Adaptive Routing for Dynamically Throttled 3-D Networks-on-Chip.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Digital spiking neuron cells for real-time reconfigurable learning networks.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Neuromorphic self-organizing map design for classification of bioelectric-timescale signals.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Energy-efficient neuromorphic receptors for wide-range temporal patterns of post-synaptic responses.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Neuromorphic spike data classifier for reconfigurable brain-machine interface.
Proceedings of the 8th International IEEE/EMBS Conference on Neural Engineering, 2017

17.5 An intrinsically linear wideband digital polar PA featuring AM-AM and AM-PM corrections through nonlinear sizing, overdrive-voltage control, and multiphase RF clocking.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
Determining Performance Boundaries on High-Level System Specifications.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

A 2.7μW 10b 640kS/s time-based A/D converter for implantable neural recording interface.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Multi-chip dataflow architecture for massive scale biophysically accurate neuron simulation.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

A real-time hybrid neuron network for highly parallel cognitive systems.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

A 2.1 μW/channel current-mode integrated neural recording interface.
Proceedings of the 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2016

A 41 μW real-time adaptive neural spike classifier.
Proceedings of the 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2016

2015
Multi-Domain SystemC model of 128-channel time-multiplexed neural interface front-end.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Ctherm: An Integrated Framework for Thermal-Functional Co-simulation of Systems-on-Chip.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Sequential power per area optimization of multichannel neural recording interface based on dual quadratic programming.
Proceedings of the 7th International IEEE/EMBS Conference on Neural Engineering, 2015

Stochastic noise analysis of neural interface front end.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Physical characterization of steady-state temperature profiles in three-dimensional integrated circuits.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Iterative learning cascaded multiclass kernel based support vector machine for neural spike data classification.
Proceedings of the IEEE Conference on Computational Intelligence in Bioinformatics and Computational Biology, 2015

Low Power Programmable Gain Analog to Digital Converter for Integrated Neural Implant Front End.
Proceedings of the Biomedical Engineering Systems and Technologies, 2015

Noise Analysis of Programmable Gain Analog to Digital Converter for Integrated Neural Implant Front End.
Proceedings of the BIODEVICES 2015, 2015

2014
Dynamic Thermal Estimation Methodology for High-Performance 3-D MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., 2014

System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs.
IEEE Trans. Very Large Scale Integr. Syst., 2014

System fault-tolerance analysis of COTS-based satellite on-board computers.
Microelectron. J., 2014

Pronto: A Low Overhead Message Passing System for High Performance Many-Core Processors.
Int. J. Netw. Comput., 2014

Parallel Channel Estimator and Equalizer for Mobile OFDM Systems.
Circuits Syst. Signal Process., 2014

Statistical power optimization of deep-submicron digital CMOS circuits based on structured perceptron.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Improving data cache performance using Persistence Selective Caching.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Cache Balancer: Access Rate and Pain Based Resource Management for Chip Multiprocessors.
Proceedings of the Second International Symposium on Computing and Networking, 2014

ESL design of customizable real-time neuron networks.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013
Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits.
J. Low Power Electron., 2013

Balanced stochastic truncation of coupled 3D interconnect.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

Low Overhead Message Passing for High Performance Many-Core Processors.
Proceedings of the First International Symposium on Computing and Networking, 2013

2012
Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element method.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A 11 µW 0°C-160°C temperature sensor in 90 nm CMOS for adaptive thermal monitoring of VLSI circuits.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Memory and computation reduction for least-square channel estimation of mobile OFDM systems.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Multi-user leo-satellite receiver for robust space detection of AIS messages.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

A Methodology for Early Exploration of TSV Placement Topologies in 3D Stacked ICs.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Selected Articles from the PATMOS 2010 Workshop.
J. Low Power Electron., 2011

High Level Synthesis of Asynchronous Circuits from Data Flow Graphs.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Systemc-AMS model of a dynamic large-scale satellite-based AIS-like network.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

A Scalable Distributed Asynchronous Control Network for High Level Synthesis of Digital Circuits.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Extracting behavior and dynamically generated hierarchy from SystemC models.
Proceedings of the 48th Design Automation Conference, 2011

2010
MB-LITE: A robust, light-weight soft-core implementation of the MicroBlaze architecture.
Proceedings of the Design, Automation and Test in Europe, 2010

2006
Design of a practical scheme for ultra wideband communication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A multistandard FFT processor for wireless system-on-chip implementations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2002
General Purpose Prototyping Platform for Data-Processor Research and Development.
Proceedings of the Field-Programmable Logic and Applications, 2002

2000
Constraints, Hurdles, and Opportunities for a Successful European Take-Up Action.
Proceedings of the Integrated Circuit Design, 2000

1994
A flexible access control mechanism for CAD frameworks.
Proceedings of the Proceedings EURO-DAC'94, 1994

1993
Aspects of realizing the CFI design representation specification in the NELSIS framework.
Proceedings of the European Design Automation Conference 1993, 1993


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