A hardware-efficient variable-length FFT processor for low-power applications. - Yifan Bo; Renfeng Dou; Jun Han 003; Xiaoyang Zeng (APSIPA, 2013)

Design of a high throughput configurable variable-length FFT processor based on switch network architecture. - Renfeng Dou; Yifan Bo; Jun Han 003; Xiaoyang Zeng (ASICON, 2013)

An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture. - Renfeng Dou; Jun Han 003; Yifan Bo; Zhiyi Yu; Xiaoyang Zeng (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation. - Jun Han 003; Renfeng Dou; Lingyun Zeng; Shuai Wang; Zhiyi Yu; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)