An improved P-admissible floorplan representation based on Corner Block List. - Renshen Wang; Sheqin Dong; Xianlong Hong (ASP-DAC, 2005)

Layer minimization of escape routing in area array packaging. - Renshen Wang; Rui Shi 003; Chung-Kuan Cheng (ICCAD, 2006)

Low Power Passive Equalizer Design for Computer Memory Links. - Ling Zhang; Wenjian Yu; Yulei Zhang 002; Renshen Wang; Alina Deutsch; George A. Katopis; Daniel M. Dreps; James F. Buckwalter; Ernest S. Kuh; Chung-Kuan Cheng (Hot Interconnects, 2008)

3-D floorplanning using labeled tree and dual sequences. - Renshen Wang; Evangeline F. Y. Young; Yi Zhu 002; Fan Chung Graham; Ronald L. Graham; Chung-Kuan Cheng (ISPD, 2008)

Noise minimization during power-up stage for a multi-domain power network. - Wanping Zhang; Yi Zhu 002; Wenjian Yu; Amirali Shayan Arani; Renshen Wang; Zhi Zhu; Chung-Kuan Cheng (ASP-DAC, 2009)

Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications. - Renshen Wang; Nan-Chi Chou; Bill Salefski; Chung-Kuan Cheng (DAC, 2009)

Octilinear redistributive routing in bump arrays. - Renshen Wang; Chung-Kuan Cheng (ACM Great Lakes Symposium on VLSI, 2009)

On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design. - Renshen Wang; Chung-Kuan Cheng (ACM Great Lakes Symposium on VLSI, 2009)

Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations. - Renshen Wang; Takumi Okamoto; Chung-Kuan Cheng (ICCD, 2009)

Physical synthesis of bus matrix for high bandwidth low power on-chip communications. - Renshen Wang; Evangeline F. Y. Young; Ronald L. Graham; Chung-Kuan Cheng (ISPD, 2010)

Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness. - Renshen Wang; Evangeline F. Y. Young; Chung-Kuan Cheng (ACM Trans. Design Autom. Electr. Syst., 2010)

Physical planning to embrace interconnect dominance in power and performance. - Renshen Wang (2010)

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications. - Renshen Wang; Yulei Zhang 002; Nan-Chi Chou; Evangeline F. Y. Young; Chung-Kuan Cheng; Ronald L. Graham (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip. - Renshen Wang; Nimish Shah (ISPD, 2012)

ROPE: Reading Order Equivariant Positional Encoding for Graph-based Document Information Extraction. - Chen-Yu Lee; Chun-Liang Li; Chu Wang; Renshen Wang; Yasuhisa Fujii; Siyang Qin; Ashok C. Popat; Tomas Pfister (ACL/IJCNLP (2), 2021)

General-Purpose OCR Paragraph Identification by Graph Convolution Networks. - Renshen Wang; Yasuhisa Fujii; Ashok C. Popat (CoRR, 2021)

FormNet: Structural Encoding beyond Sequential Modeling in Form Document Information Extraction. - Chen-Yu Lee; Chun-Liang Li; Timothy Dozat; Vincent Perot; Guolong Su; Nan Hua; Joshua Ainslie; Renshen Wang; Yasuhisa Fujii; Tomas Pfister (ACL (1), 2022)

Unified Line and Paragraph Detection by Graph Convolutional Networks. - Shuang Liu; Renshen Wang; Michalis Raptis; Yasuhisa Fujii (DAS, 2022)

Post-OCR Paragraph Recognition by Graph Convolutional Networks. - Renshen Wang; Yasuhisa Fujii; Ashok C. Popat (WACV, 2022)

FormNetV2: Multimodal Graph Contrastive Learning for Form Document Information Extraction. - Chen-Yu Lee; Chun-Liang Li; Hao Zhang; Timothy Dozat; Vincent Perot; Guolong Su; Xiang Zhang; Kihyuk Sohn; Nikolay Glushnev; Renshen Wang; Joshua Ainslie; Shangbang Long; et al. (ACL (1), 2023)

Text Reading Order in Uncontrolled Conditions by Sparse Graph Segmentation. - Renshen Wang; Yasuhisa Fujii; Alessandro Bissacco (ICDAR (6), 2023)