Design guidance in the power dimension. - Jan M. Rabaey; Lisa M. Guerra; Renu Mehra (ICASSP, 1995)

Optimizing power using transformations. - Anantha P. Chandrakasan; Miodrag Potkonjak; Renu Mehra; Jan M. Rabaey; Robert W. Brodersen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Exploiting regularity for low-power design. - Renu Mehra; Jan M. Rabaey (ICCAD, 1996)

An Integrated CAD Environment for Low-Power Design. - Paul E. Landman; Renu Mehra; Jan M. Rabaey (IEEE Des. Test Comput., 1996)

Low-power architectural synthesis and the impact of exploiting locality. - Renu Mehra; Lisa M. Guerra; Jan M. Rabaey (J. VLSI Signal Process., 1996)

A partitioning scheme for optimizing interconnect power. - Renu Mehra; Lisa M. Guerra; Jan M. Rabaey (IEEE J. Solid State Circuits, 1997)

Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths. - Michael Münch; Norbert Wehn; Bernd Wurth; Renu Mehra; Jim Sproch (DATE, 2000)

RTL c-based methodology for designing and verifying a multi-threaded processor. - Luc Séméria; Renu Mehra; Barry M. Pangrle; Arjuna Ekanayake; Andrew Seawright; Daniel Ng (DAC, 2002)

Industry focus session on low-power design. - Clive Bittlestone; Jim Kardach; Renu Mehra; David Flynn; Barry M. Pangrle (ISLPED, 2012)

Commercial low-power EDA tools: a review. - Renu Mehra (ISLPED, 2012)

Message from the general chairs. - Luca Benini; Renu Mehra; Mauro Olivieri (ISLPED, 2015)