Compaction of ATPG-generated test sequences for sequential circuits. - Rabindra K. Roy; Thomas M. Niermann; Janak H. Patel; Jacob A. Abraham; Resve A. Saleh (ICCAD, 1988)

The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation. - Resve A. Saleh; A. Richard Newton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Parallel Circuit Simulation Using Hierarchical Relaxation. - Gih-Guang Hung; Yen-Cheng Wen; Kyle A. Gallivan; Resve A. Saleh (DAC, 1990)

Mixed-Mode Incremental Simulation and Concurrent Fault Simulation. - Yun-Cheng Ju; Fred L. Yang; Resve A. Saleh (ICCAD, 1990)

Accelerating relaxation algorithms for circuit simulation using waveform-Newton and step-size refinement. - Resve A. Saleh; Jacob K. White 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Simulation techniques for mixed analog/digital circuits. - Eduardo L. Acuna; James P. Dervenis; Andrew J. Pagones; Fred L. Yang; Resve A. Saleh (IEEE J. Solid State Circuits, 1990)

Incremental Techniques for the Identification of Statically Sensitizable Critical Paths. - Yun-Cheng Ju; Resve A. Saleh (DAC, 1991)

iMACSIM: A Program for Multi-Level Analog Circuit Simulation. - Jaidip Singh; Resve A. Saleh (ICCAD, 1991)

Identification of Viable Paths Using Binary Decision Diagrams. - Yun-Cheng Ju; Resve A. Saleh (ICCD, 1991)

Parallel Event-Driven Waveform Relaxation. - Yen-Cheng Wen; Kyle A. Gallivan; Resve A. Saleh (ICCD, 1991)

Consistency checking and optimization of macromodels. - Yun-Cheng Ju; Vasant B. Rao; Resve A. Saleh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Incremental Circuit Simulation Using Waveform Relaxation. - Yun-Cheng Ju; Resve A. Saleh (DAC, 1992)

Exact Evaluation of Diagnostic Test Resolution. - Ken Kubiak; Steven Parkes; W. Kent Fuchs; Resve A. Saleh (DAC, 1992)

Parallel waveform-Newton algorithms for circuit simulation. - Eugene Z. Xia; Resve A. Saleh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Simulation and analysis of transient faults in digital circuits. - Fred L. Yang; Resve A. Saleh (IEEE J. Solid State Circuits, 1992)

Improving the performance of parallel relaxation-based circuit simulators. - Gih-Guang Hung; Yen-Cheng Wen; Kyle A. Gallivan; Resve A. Saleh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Mixed-mode simulation and analog multilevel simulation. - Resve A. Saleh; Shyh-Jye Jou; A. Richard Newton (Kluwer, 1994)

Improving Parallel Circuit Simulation Using High-Level Waveforms. - Yen-Cheng Wen; Kyle A. Gallivan; Resve A. Saleh (ISCAS, 1995)

A multifrequency technique for frequency response computation with application to switched-capacitor circuits with nonlinearities. - Jeffrey G. Mueller; Brian A. A. Antao; Resve A. Saleh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Multilevel and mixed-domain simulation of analog circuits and systems. - Resve A. Saleh; Brian A. A. Antao; Jaidip Singh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Full-chip verification of UDSM designs. - Resve A. Saleh; David Overhauser; Sandy Taylor (ICCAD, 1998)

Clock skew verification in the presence of IR-drop in the powerdistribution network. - Resve A. Saleh; Syed Zakir Hussain; Steffen Rochel; David Overhauser (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Trends in Low Power Digital System-on-Chip Designs (invited). - Resve A. Saleh; G. Lim; T. Kadowaki; K. Uchiyama (ISQED, 2002)

Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores. - Mohsen Nahvi; André Ivanov; Resve A. Saleh (ITC, 2002)

SoC implementation issues for synthesizable embedded programmable logic cores. - James C. H. Wu; Victor O. Aken'Ova; Steven J. E. Wilton; Resve A. Saleh (CICC, 2003)

Analog IP design flow for SoC applications. - Mama Hamour; Resve A. Saleh; Shahriar Mirabbasi; André Ivanov (ISCAS (4), 2003)

Design of a switch for network on chip applications. - Partha Pratim Pande; Cristian Grecu; André Ivanov; Res Saleh (ISCAS (5), 2003)

A technique for DC-offset removal and carrier phase error compensation in integrated wireless receivers. - Stephan Shang; Shahriar Mirabbasi; Resve A. Saleh (ISCAS (1), 2003)

Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs. - Cristian Grecu; Partha Pratim Pande; André Ivanov; Res Saleh (ACM Great Lakes Symposium on VLSI, 2004)

A Scalable Communication-Centric SoC Interconnect Architecture. - Cristian Grecu; Partha Pratim Pande; André Ivanov; Res Saleh (ISQED, 2004)

An improved "soft" eFPGA design and implementation strategy. - Victor O. Aken'Ova; Guy Lemieux; Resve A. Saleh (CICC, 2005)

Methodologies and Algorithms for Testing Switch-Based NoC Interconnects. - Cristian Grecu; Partha Pratim Pande; Baosheng Wang; André Ivanov; Res Saleh (DFT, 2005)

Effect of traffic localization on energy dissipation in NoC-based interconnect. - Partha Pratim Pande; Cristian Grecu; Michael Jones; André Ivanov; Res Saleh (ISCAS (2), 2005)

Power-Delay Metrics Revisited for 90nm CMOS Technology. - Dipanjan Sengupta; Resve A. Saleh (ISQED, 2005)

Design, Synthesis, and Test of Networks on Chips. - Partha Pratim Pande; Cristian Grecu; André Ivanov; Resve A. Saleh; Giovanni De Micheli (IEEE Des. Test Comput., 2005)

An approach that will NoC your SoCs off! - Resve A. Saleh (IEEE Des. Test Comput., 2005)

Timing analysis of network on chip architectures for MP-SoC platforms. - Cristian Grecu; Partha Pratim Pande; André Ivanov; Res Saleh (Microelectron. J., 2005)

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. - Partha Pratim Pande; Cristian Grecu; Michael Jones; André Ivanov; Resve A. Saleh (IEEE Trans. Computers, 2005)

NoC Interconnect Yield Improvement Using Crosspoint Redundancy. - Cristian Grecu; André Ivanov; Res Saleh; Partha Pratim Pande (DFT, 2006)

On-line Fault Detection and Location for NoC Interconnects. - Cristian Grecu; André Ivanov; Res Saleh; Egor S. Sogomonyan; Partha Pratim Pande (IOLTS, 2006)

Testable and self-repairable structured logic design. - Uthman Alsaiari; Resve A. Saleh (ISCAS, 2006)

A high-speed low-energy dynamic PLA using an input-isolation scheme. - Reza Molavi; Shahriar Mirabbasi; Resve A. Saleh (ISCAS, 2006)

Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology. - Xiongfei Meng; Resve A. Saleh; Karim Arabi (ISQED, 2006)

Fast Configuration of an Energy-Efficient Branch Predictor. - Peter Hallschmid; Resve A. Saleh (ISVLSI, 2006)

A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm. - Victor O. Aken'Ova; Resve A. Saleh (ISVLSI, 2006)

BIST for Network-on-Chip Interconnect Infrastructures. - Cristian Grecu; Partha Pratim Pande; André Ivanov; Res Saleh (VTS, 2006)

System-on-Chip: Reuse and Integration. - Resve A. Saleh; Steven J. E. Wilton; Shahriar Mirabbasi; Alan J. Hu; Mark R. Greenstreet; Guy Lemieux; Partha Pratim Pande; Cristian Grecu; André Ivanov (Proc. IEEE, 2006)

The application of complex quantized feedback in integrated wireless receivers. - Zahra Sadat Ebadi; Shahriar Mirabbasi; Resve A. Saleh (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling. - Peter Hallschmid; Resve A. Saleh (DAC, 2007)

Essential Fault-Tolerance Metrics for NoC Infrastructures. - Cristian Grecu; Lorena Anghel; Partha Pratim Pande; André Ivanov; Resve A. Saleh (IOLTS, 2007)

Power Reduction of On-Chip Serial Links. - Amit Kedia; Resve A. Saleh (ISCAS, 2007)

A Novel Active Decoupling Capacitor Design in 90nm CMOS. - Xiongfei Meng; Karim Arabi; Resve A. Saleh (ISCAS, 2007)

Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy. - Uthman Alsaiari; Resve A. Saleh (ISQED, 2007)

DFM-EDA's Salvation or its Excuse for Being out of Touch with Engineering? - Resve A. Saleh; Pallab K. Chatterjee; Ivan Pesic; Robbert Dobkins; Mike Smayling; Joseph Sawicki (ISQED, 2007)

Power Supply Noise in SoCs: Metrics, Management, and Measurement. - Karim Arabi; Resve A. Saleh; Xiongfei Meng (IEEE Des. Test Comput., 2007)

Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip. - Zahra Sadat Ebadi; Alireza Nasiri Avanaki; Resve A. Saleh; André Ivanov (Integr., 2007)

Testing Network-on-Chip Communication Fabrics. - Cristian Grecu; André Ivanov; Resve A. Saleh; Partha Pratim Pande (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Generalized Power-Delay Metrics in Deep Submicron CMOS Designs. - Dipanjan Sengupta; Resve A. Saleh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Application-driven floorplan-aware voltage island design. - Dipanjan Sengupta; Resve A. Saleh (DAC, 2008)

Delay macromodeling and estimation for RTL. - Tatsuya Koyagi; Masahiro Fukui; Resve A. Saleh (ISCAS, 2008)

Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits. - Uthman Alsaiari; Resve A. Saleh (ISQED, 2008)

A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS. - Zahra Sadat Ebadi; Resve A. Saleh (ISQED, 2008)

A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks. - Jeff Mueller; Resve A. Saleh (ISQED, 2008)

Supply voltage selection in Voltage Island based SoC design. - Dipanjan Sengupta; Resve A. Saleh (SoCC, 2008)

Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance. - Jeff Mueller; Resve A. Saleh (VLSI Design, 2008)

Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs. - Peter Hallschmid; Resve A. Saleh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Adaptive Compensation of RF Front-End Nonidealities in Direct Conversion Receivers. - Zahra Sadat Ebadi; Resve A. Saleh (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS. - Xiongfei Meng; Resve A. Saleh; Karim Arabi (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Charge-borrowing decap: A novel circuit for removal of local supply noise violations. - Xiongfei Meng; Resve A. Saleh; Steven J. E. Wilton (CICC, 2009)

PVT variation impact on voltage island formation in MPSoC design. - Sohaib Majzoub; Resve A. Saleh; Rabab K. Ward (ISQED, 2009)

Active decap design considerations for optimal supply noise reduction. - Xiongfei Meng; Resve A. Saleh (ISQED, 2009)

Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms. - Sohaib Majzoub; Resve A. Saleh; Steven J. E. Wilton; Rabab Ward (SoC, 2009)

Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT. - Sohaib Majzoub; Resve A. Saleh; Steven J. E. Wilton; Rabab Kreidieh Ward (SoCC, 2009)

An Improved Active Decoupling Capacitor for "Hot-Spot" Supply Noise Reduction in ASIC Designs. - Xiongfei Meng; Resve A. Saleh (IEEE J. Solid State Circuits, 2009)

Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design. - Dipanjan Sengupta; Resve A. Saleh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm. - Sohaib Majzoub; Resve A. Saleh; Steven J. E. Wilton; Rabab K. Ward (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Sequence pair based voltage island floorplanning. - Dipanjan Sengupta; Andreas G. Veneris; Steven J. E. Wilton; André Ivanov; Res Saleh (IGCC, 2011)

RTL delay macro-modeling with Vt and Vdd variability. - Tatsuya Koyagi; Sohaib Majzoub; Masahiro Fukui; Resve A. Saleh (IDT, 2011)

A 10 Gb/s low-power serdes receiver based on a hybrid speculative/SAR digitization technique. - Arash Zargaran-Yazd; Shahriar Mirabbasi; Res Saleh (ISCAS, 2011)

Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations. - Jeffrey G. Mueller; Resve A. Saleh (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era. - Sohaib Majzoub; Resve A. Saleh; Imran Ashraf; Mottaqiallah Taouil; Said Hamdioui (IEEE Access, 2019)

Solution to the Non-Monotonicity and Crossing Problems in Quantile Regression. - Resve A. Saleh; A. K. Md. Ehsanes Saleh (CoRR, 2021)

Rapid Design-Space Exploration for Low-Power Manycores Under Process Variation Utilizing Machine Learning. - Sohaib Majzoub; Resve A. Saleh; Mottaqiallah Taouil; Said Hamdioui; Mohamed Bamakhrama (IEEE Access, 2022)

Statistical Properties of the log-cosh Loss Function Used in Machine Learning. - Resve A. Saleh; A. K. Md. Ehsanes Saleh (CoRR, 2022)