Othello Solver based on a soft-core MIMD processor array. - Takayuki Mabuchi; Takahiro Watanabe; Retsu Moriwaki; Yuji Aoyama; Amarjargal Gundjalam; Yuichiro Yamaji; Hironari Nakada; Minoru Watanabe (FPT, 2010)

An FPGA Connect6 Solver with a two-stage pipelined evaluation. - Takahiro Watanabe; Retsu Moriwaki; Yuichiro Yamaji; Yuki Kamikubo; Yuki Torigai; Yuki Nihira; Takashi Yoza; Yumiko Ueno; Yuji Aoyama; Minoru Watanabe (FPT, 2011)

FPGA Blokus Duo Solver using a massively parallel architecture. - Takashi Yoza; Retsu Moriwaki; Yuki Torigai; Yuki Kamikubo; Takayuki Kubota; Takahiro Watanabe; Takumi Fujimori; Hiroyuki Ito; Masato Seo; Kouta Akagi; Yuichiro Yamaji; Minoru Watanabe (FPT, 2013)

Optically reconfigurable gate array with an angle-multiplexed holographic memory. - Retsu Moriwaki; Hikaru Maekawa; Akifumi Ogiwara; Minoru Watanabe (ACM Great Lakes Symposium on VLSI, 2014)

Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array. - Retsu Moriwaki; Hiroyuki Ito; Kouta Akagi; Minoru Watanabe; Akifumi Ogiwara (ARC, 2015)