Stability Analysis of High-order Modulators for Delta-Sigma ADCs. - Rex T. Baird; Terri S. Fiez (ISCAS, 1993)

Improved Delta-Sigma DAC Linearity Using Data Weighted Averaging. - Rex T. Baird; Terri S. Fiez (ISCAS, 1995)

A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multibit DAC. - Rex T. Baird; Terri S. Fiez (IEEE J. Solid State Circuits, 1996)

A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter. - Michael H. Perrott; Yunteng Huang; Rex T. Baird; Bruno W. Garlepp; Ligang Zhang; Jerrell P. Hein (ISSCC, 2006)

A 2.5-Gb/s Multi-Rate 0.25-$ mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition. - Michael H. Perrott; Yunteng Huang; Rex T. Baird; Bruno W. Garlepp; Douglas Pastorello; Eric T. King; Qicheng Yu; Dan B. Kasha; Philip Steiner; Ligang Zhang; Jerrell P. Hein; Bruce Del Signore (IEEE J. Solid State Circuits, 2006)