Ultra high speed Full Adders. - Keivan Navi; Reza Faghih Mirzaee; Mohammad Hossein Moaiyeri; Babak Mazloom Nezhad; Omid Hashemipour; K. Shams (IEICE Electron. Express, 2008)

Two New Low-Power and High-Performance Full Adders. - Mohammad Hossein Moaiyeri; Reza Faghih Mirzaee; Keivan Navi (J. Comput., 2009)

Two new low-power Full Adders based on majority-not gates. - Keivan Navi; Mohammad Hossein Moaiyeri; Reza Faghih Mirzaee; Omid Hashemipour; Babak Mazloom Nezhad (Microelectron. J., 2009)

Design of an ASIP IDEA crypto processor. - Reza Faghih Mirzaee; Mohammad Eshghi (NESEA, 2011)

High-speed full adder based on minority function and bridge style for nanoscale. - Keivan Navi; Horialsadat Hossein Sajedi; Reza Faghih Mirzaee; Mohammad Hossein Moaiyeri; Ali Jalali; Omid Kavehei (Integr., 2011)

A New Robust and High-Performance Hybrid Full Adder Cell. - Reza Faghih Mirzaee; Mohammad Hossein Moaiyeri; Hamid Khorsand; Keivan Navi (J. Circuits Syst. Comput., 2011)

Dramatically Low-Transistor-Count High-Speed Ternary Adders. - Reza Faghih Mirzaee; Mohammad Hossein Moaiyeri; Mojtaba Maleknejad; Keivan Navi; Omid Hashemipour (ISMVL, 2013)

A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits. - Mohammad Hossein Moaiyeri; Reza Faghih Mirzaee; Akbar Doostaregan; Keivan Navi; Omid Hashemipour (IET Comput. Digit. Tech., 2013)

Design, analysis, and implementation of partial product reduction phase by using wide m: 3 (4 ≤ m ≤ 10) compressors. - Shima Mehrabi; Reza Faghih Mirzaee; Sharareh Zamanzadeh; Keivan Navi; Omid Hashemipour (Int. J. High Perform. Syst. Archit., 2013)

Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic. - Reza Faghih Mirzaee; Tooraj Nikoubin; Keivan Navi; Omid Hashemipour (Microelectron. J., 2013)

Optimized Adder Cells for Ternary Ripple-Carry Addition. - Reza Faghih Mirzaee; Keivan Navi (IEICE Trans. Inf. Syst., 2014)

A Systematic Approach to Design Boolean Functions using CNFETs and an Array of CNFET capacitors. - Mojtaba Maleknejad; Reza Faghih Mirzaee; Keivan Navi; Akbar Dargahi (J. Circuits Syst. Comput., 2014)

High-Efficient Circuits for Ternary Addition. - Reza Faghih Mirzaee; Keivan Navi; Nader Bagherzadeh (VLSI Design, 2014)

Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic. - Masoomeh Jasemi; Reza Faghih Mirzaee; Keivan Navi; Nader Bagherzadeh (IET Circuits Devices Syst., 2015)

A novel low-energy CNFET-based full adder cell using pass-transistor logic. - Yavar Safaei Mehrabani; Reza Faghih Mirzaee; Mohammad Eshghi (Int. J. High Perform. Syst. Archit., 2015)

New dynamic ternary minimum and maximum circuits with reduced switching activity and without any additional voltage sources. - Shirin Rezaie; Reza Faghih Mirzaee; Keivan Navi; Omid Hashemipour (Int. J. High Perform. Syst. Archit., 2015)

New Current-Mode Integrated Ternary Min/Max Circuits without Constant Independent Current Sources. - Mona Moradi; Reza Faghih Mirzaee; Keivan Navi (J. Electr. Comput. Eng., 2015)

Ternary Versus Binary Multiplication with Current-Mode CNTFET-Based K-Valued Converters. - Mona Moradi; Reza Faghih Mirzaee; Keivan Navi (ISMVL, 2016)

Design of a Ternary Edge-Triggered D Flip-Flap-Flop for Multiple-Valued Sequential Logic. - Reza Faghih Mirzaee; Niloofar Farahani (CoRR, 2016)

New Current-Mode Multipliers by CNTFET-Based n-Valued Binary Converters. - Mona Moradi; Reza Faghih Mirzaee; Keivan Navi (IEICE Trans. Electron., 2016)

Ternary cyclic redundancy check by a new hardware-friendly ternary operator. - Mahya Sam Daliri; Reza Faghih Mirzaee; Keivan Navi; Nader Bagherzadeh (Microelectron. J., 2016)

Physical Unclonable Functions Based on Carbon Nanotube FETs. - Mona Moradi; Sha Tao; Reza Faghih Mirzaee (ISMVL, 2017)

A new approach for designing compressors with a new hardware-friendly mathematical method for multi-input XOR gates. - Mahya Sam Daliri; Keivan Navi; Reza Faghih Mirzaee; Nader Bagherzadeh (IET Circuits Devices Syst., 2017)

High-performance ternary operators for scrambling. - Mahya Sam Daliri; Reza Faghih Mirzaee; Keivan Navi; Nader Bagherzadeh (Integr., 2017)

A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector. - Yavar Safaei Mehrabani; Reza Faghih Mirzaee; Zahra Zareei; Seyedeh Mohtaram Daryabari (J. Circuits Syst. Comput., 2017)

Design of a Ternary Edge-Sensitive D FFF for Multiple-Valued Sequential Logic. - Reza Faghih Mirzaee; Niloofar Farahani (J. Low Power Electron., 2017)

A Single Parity-Check Digit for One Trit Error Detection in Ternary Communication Systems: Gate-Level and Transistor-Level Designs. - Reza Faghih Mirzaee; Mahya Sam Daliri; Keivan Navi; Nader Bagherzadeh (J. Multiple Valued Log. Soft Comput., 2017)

Non-preemptive offline multi-job mapping for a photonic network on a chip. - Akram Reza; Reza Faghih Mirzaee (Nano Commun. Networks, 2017)

Applicability of Partial Ternary Full Adder in Ternary Arithmetic Units. - Aida Ghorbani Asibelagh; Reza Faghih Mirzaee (CoRR, 2019)

MIPS-Core Application Specific Instruction-Set Processor for IDEA Cryptography - Comparison between Single-Cycle and Multi-Cycle Architectures. - Ahmad Ahmadi; Reza Faghih Mirzaee (CoRR, 2019)

Analytical Review of Noise Margin in MVL: Clarification of a Deceptive Matter. - Mehdi Takbiri; Reza Faghih Mirzaee; Keivan Navi (Circuits Syst. Signal Process., 2019)

Partial product generation for unbalanced ternary signed multiplication. - Samira Din Mohammadi; Reza Faghih Mirzaee; Keivan Navi (Int. J. High Perform. Syst. Archit., 2019)

Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source. - Nooshin Azimi; Reza Faghih Mirzaee; Keivan Navi; Amir Masoud Rahmani (IET Comput. Digit. Tech., 2020)

Multi valued parity generator based on Sudoku tables: properties and detection probability. - Shahab Ghalamdoost Pirbazari; Alireza Souri; Reza Faghih Mirzaee; Sam Jabbehdari (IET Commun., 2020)

A Universal Method for Designing Multi-Digit Ternary to Binary Converter Using CNTFET. - Maryam Shahangian; Seied Ali Hosseini; Reza Faghih Mirzaee (J. Circuits Syst. Comput., 2020)

Ultra-Fast, High-Performance 8x8 Approximate Multipliers by a New Multicolumn 3, 3: 2 Inexact Compressor and its Derivatives. - Fereshteh Karimi; Reza Faghih Mirzaee; Ali Fakeri-Tabrizi; Arman Roohi (CoRR, 2021)

Two Novel Current-Mode CNFET-Based Full Adders Using ULPD as Voltage Regulator. - Hamidreza Uoosefian; Keivan Navi; Reza Faghih Mirzaee; Mehdi Hosseinzadeh 001 (J. Circuits Syst. Comput., 2021)

High-performance quaternary latch and D-Type flip-flop with selective outputs. - Fatemeh Safipoor; Reza Faghih Mirzaee; Mahdi Zare (Microelectron. J., 2021)

Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement. - Mehdi Takbiri; Keivan Navi; Reza Faghih Mirzaee (IEEE Access, 2022)

Towards effective offloading mechanisms in fog computing. - Maryam Sheikh Sofla; Mostafa Haghi Kashani; Ebrahim Mahdipour; Reza Faghih Mirzaee (Multim. Tools Appl., 2022)

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments. - Sarina Nemati; Mostafa Haghi Kashani; Reza Faghih Mirzaee (IET Circuits Devices Syst., 2023)

Design and evaluation of ultra-fast 8-bit approximate multipliers using novel multicolumn inexact compressors. - Fereshteh Karimi; Reza Faghih Mirzaee; Ali Fakeri-Tabrizi; Arman Roohi (Int. J. Circuit Theory Appl., 2023)

Design of new low-power and high-speed quaternary flip-flops based on CNTFETs. - Majid Jafari; Samira Sayedsalehi; Reza Faghih Mirzaee; Razieh Farazkish (Comput. Electr. Eng., 2024)

DAFA: Dynamic approximate full adders for high area and energy efficiency. - Yavar Safaei Mehrabani; Reza Faghih Mirzaee (Integr., 2024)

Adaptive multi-beltway thermal-aware routing algorithm for 3D NoC system. - Mohammad Reza Dadmand; Razieh Farazkish; Akram Reza; Roshanak Rafiei Nazari; Reza Faghih Mirzaee (J. Supercomput., 2025)