CuPAN - High Throughput On-chip Interconnection for Neural Networks. - Ali Yasoubi; Reza Hojabr; Hengameh Takshi; Mehdi Modarressi; Masoud Daneshtalab (ICONIP (3), 2015)

Power-Efficient Accelerator Design for Neural Networks Using Computation Reuse. - Ali Yasoubi; Reza Hojabr; Mehdi Modarressi (IEEE Comput. Archit. Lett., 2017)

Customizing Clos Network-on-Chip for Neural Networks. - Reza Hojabr; Mehdi Modarressi; Masoud Daneshtalab; Ali Yasoubi; Ahmad Khonsari (IEEE Trans. Computers, 2017)

Using Residue Number Systems to Accelerate Deterministic Bit-stream Multiplication. - Kamyar Givaki; Reza Hojabr; M. Hassan Najafi; Ahmad Khonsari; M. Hossein Gholamrezayi; Saeid Gorgin 001; Dara Rahmati (ASAP, 2019)

SkippyNN: An Embedded Stochastic-Computing Accelerator for Convolutional Neural Networks. - Reza Hojabr; Kamyar Givaki; S. M. Reza Tayaranian; Parsa Esfahanian; Ahmad Khonsari; Dara Rahmati; M. Hassan Najafi (DAC, 2019)

μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators. - Amirali Sharifian; Reza Hojabr; Navid Rahimi; Sihao Liu; Apala Guha; Tony Nowatzki; Arrvindh Shriraman (MICRO, 2019)

TaxoNN: A Light-Weight Accelerator for Deep Neural Network Training. - Reza Hojabr; Kamyar Givaki; Kossar Pourahmadi; Parsa Nooralinejad; Ahmad Khonsari; Dara Rahmati; M. Hassan Najafi (ISCAS, 2020)

On the Resilience of Deep Learning for Reduced-voltage FPGAs. - Kamyar Givaki; Behzad Salami 001; Reza Hojabr; S. M. Reza Tayaranian; Ahmad Khonsari; Dara Rahmati; Saeid Gorgin 001; Adrián Cristal; Osman S. Unsal (PDP, 2020)

Real-Time Formal Verification of Autonomous Systems With An FPGA. - Minh Bui; Michael Lu; Reza Hojabr; Mo Chen; Arrvindh Shriraman (CoRR, 2020)

X-Layer: Building Composable Pipelined Dataflows for Low-Rank Convolutions. - Naveen Vedula; Reza Hojabr; Ahmad Khonsari; Arrvindh Shriraman (PACT, 2021)

SPAGHETTI: Streaming Accelerators for Highly Sparse GEMM on FPGAs. - Reza Hojabr; Ali Sedaghati; Amirali Sharifian; Ahmad Khonsari; Arrvindh Shriraman (HPCA, 2021)

Real-Time Hamilton-Jacobi Reachability Analysis of Autonomous System With An FPGA. - Minh Bui; Michael Lu; Reza Hojabr; Mo Chen 001; Arrvindh Shriraman (IROS, 2021)

High-Performance Deterministic Stochastic Computing Using Residue Number System. - Kamyar Givaki; Reza Hojabr; MohammadHosein Gholamrezaei; Ahmad Khonsari; Saeid Gorgin 001; Dara Rahmati; M. Hassan Najafi (IEEE Des. Test, 2021)

mu-grind: A Framework for Dynamically Instrumenting HLS-Generated RTL. - Parmida Vahdatniya; Amirali Sharifian; Reza Hojabr; Arrvindh Shriraman (PACT, 2022)

X-cache: a modular architecture for domain-specific caches. - Ali Sedaghati; Milad Hakimi; Reza Hojabr; Arrvindh Shriraman (ISCA, 2022)