Design and implementation of an enhanced on chip mesh router. - Manel Langar; Riad Bourguiba; Jaouhar Mouine (SSD, 2015)

Implementation of a baseline RISC for the realization of a dynamically reconfigurable processor. - Hajer Najjar; Riad Bourguiba; Jaouhar Mounie (SSD, 2015)

Virtual channel router architecture for Network on Chip with adaptive inter-port buffers sharing. - Manel Langar; Riad Bourguiba; Jaouhar Mouine (SSD, 2016)

A new programmable ALU architecture for hard-core processor. - Hajer Najjar; Riad Bourguiba; Jaouhar Mouine (SSD, 2016)

Design and implementation of a fall detection system on a Zynq board. - Sahar Abdelhedi; Mouna Baklouti; Riad Bourguiba; Jaouhar Mouine (AICCSA, 2016)

Vivado HLS-based implementation of a fall detection decision core on an FPGA platform. - Sahar Abdelhedi; Mouna Baklouti; Riad Bourguiba; Jaouhar Mouine (IDT, 2016)

Development of a two-threshold-based fall detection algorithm for elderly health monitoring. - Sahar Abdelhedi; Riad Bourguiba; Jaouhar Mouine; Mouna Baklouti (RCIS, 2016)

Buffers Sharing Switch Design Exploiting Dynamic Traffic Orientation in a NoC. - Manel Lanzar; Riad Bourguiba; Jaouhar Mouine (SSD, 2018)

A Reusable Hybrid RISC Processor with Programmable Instruction Set. - Hajer Najjar; Riad Bourguiba; Jaouhar Mouine (SSD, 2018)