DF-DICE: a scalable solution for soft error tolerant circuit design. - Riaz Naseer; Jeff Draper (ISCAS, 2006)

Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology. - Riaz Naseer; Jeff Draper; Younes Boulghassoul; Sandeepan DasGupta; Art Witulski (ACM Great Lakes Symposium on VLSI, 2007)

Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM. - Riaz Naseer; Younes Boulghassoul; Jeff Draper; Sandeepan DasGupta; Art Witulski (ISCAS, 2007)

Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs. - Riaz Naseer; Jeff Draper (ESSCIRC, 2008)

DEC ECC design to improve memory reliability in Sub-100nm technologies. - Riaz Naseer; Jeff Draper (ICECS, 2008)