Microelectronics Education using WWW and CAD Tools. - Ricardo Reis 001; Leandro Soares Indrusiak (SBCCI, 1998)

A Case Study for a WWW based CAD Framework. - Leandro Soares Indrusiak; Ricardo Reis 001 (SBCCI, 1998)

An Improved Path Enumeration Method Considering Different Fall and Rise Gate Delays. - José Luís Güntzel; Ana Cristina Medina Pinto; Fernando Moraes 001; Ricardo Reis 001 (SBCCI, 1998)

Designing a Mask Programmable Matrix for Sequential Circuits. - Fernanda Lima 001; Marcelo O. Johann; José Luís Almada Güntzel; Eduardo D'Avila; Luigi Carro; Ricardo Augusto da Luz Reis (VLSI, 1999)

Microelectronics Education Using WWW. - Ricardo Augusto da Luz Reis; Leandro Soares Indrusiak (MSE, 1999)

VRML and Microelectronics Education. - Ricardo Augusto da Luz Reis; Leandro Soares Indrusiak (MSE, 1999)

A frame stream controller IP. - Fernanda Gusmão de Lima; Marcelo Barcelos; Juergen Rochol; Sergio Bampi; Ricardo Reis 001 (ISCAS, 2000)

A Self-Testing Mask Programmable Matrix Using Built-in Current Sensing. - Fernanda Gusmão de Lima; Eduardo D'Avila; Mauricio Moraes; Marcelo Lubaszewski; Ricardo Reis 001 (LATW, 2000)

Structuring Web course pages as Automata: revising concepts. - Júlio Henrique Araújo Pereira Machado; Carlos Tadeu Q. de Morais; Paulo Blauth Menezes; Ricardo Reis 001 (RIAO, 2000)

SisECO: Design of an Echo-Canceling IC for Base Band Modems. - Luciano Agostini; Georg Stemmer; A. Prado; Roberto Pacheco; T. Campos; Sergio Bampi; Ricardo Reis 001 (SBCCI, 2000)

LASCA-Interconnect Parasitic Extraction Tool for Deep-Submicron IC Design. - F. K. Ferreira; Fernando Moraes 001; Ricardo Reis 001 (SBCCI, 2000)

WTROPIC: A WWW-Based Macro-Cell Generator. - João Leonardo Fragoso; Fernando Moraes 001; Ricardo Reis 001 (SBCCI, 2000)

ATG-Based Timing Analysis of Circuits Containing Complex Gates. - José Luís Güntzel; Ana Cristina Medina Pinto; Eduardo D'Avila; Ricardo Reis 001 (SBCCI, 2000)

From a Hyperdocument-Centric to an Object-Oriented Approach for the Cave Project. - Leandro Soares Indrusiak; Ricardo Augusto da Luz Reis (SBCCI, 2000)

Net by Net Routing with a New Path Search Algorithm. - Marcelo O. Johann; Ricardo Reis 001 (SBCCI, 2000)

Designing a Radiation Hardened 8051-Like Micro-Controller. - Fernanda Gusmão de Lima; Érika F. Cota; Luigi Carro; Marcelo Lubaszewski; Ricardo Reis 001; Raoul Velazco; Sana Rezgui (SBCCI, 2000)

Admissibility Proofs for the LCS* Algorithm. - Marcelo O. Johann; Andrew E. Caldwell; Ricardo Augusto da Luz Reis; Andrew B. Kahng (IBERAMIA-SBIA, 2000)

Specification and design of an Ethernet Interface soft IP. - João Leonardo Fragoso; Eduardo Costa Pereira; Juergen Rochol; Sergio Bampi; Ricardo Reis 001 (J. Braz. Comput. Soc., 2000)

Distributed Collaborative Design over Cave2 Framework. - Leandro Soares Indrusiak; Jürgen Becker 001; Manfred Glesner; Ricardo Augusto da Luz Reis (VLSI-SOC, 2001)

A Timed Calculus for ATG-Based Timing Analysis with Complex Gates. - José Luís Güntzel; Ana Cristina Medina Pinto; Ricardo Reis 001 (LATW, 2001)

LEGAL: An Algorithm for Simultaneous Net Routing. - Marcelo de Oliveira Johann; Ricardo Augusto da Luz Reis (SBCCI, 2001)

Interconnection Length Estimation at Logic-Level. - João Baptista dos Santos Martins; Fernando Moraes 001; Ricardo Reis 001 (SBCCI, 2001)

Jale3D - Platform-independent IC/MEMS Layout Edition Tool. - Luciano Copello Ost; Marcos Mainardi; Leandro Soares Indrusiak; Ricardo Reis 001 (SBCCI, 2001)

Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults. - Érika F. Cota; Fernanda Lima 001; Sana Rezgui; Luigi Carro; Raoul Velazco; Marcelo Lubaszewski; Ricardo Reis 001 (J. Electron. Test., 2001)

3D integrated circuit layout visualization using VRML. - Leandro Soares Indrusiak; Ricardo Augusto da Luz Reis (Future Gener. Comput. Syst., 2001)

Análise de Timing Funcional de Circuitos VLSI Contendo Portas Complexas. - José Luís Almada Güntzel; Ricardo Augusto da Luz Reis (RITA, 2001)

Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments. - Leandro Soares Indrusiak; Manfred Glesner; Ricardo Augusto da Luz Reis (DATE, 2002)

Computing: The Shape of an Evolving Discipline. - Lillian N. Cassel; Gordon Davies; Deepak Kumar 002; Ralf Denzer; A. E. N. Hacquebard; Richard J. LeBlanc; Luiz Ernesto Merkle; Fred Mulder; Zeljko Panian; Ricardo Augusto da Luz Reis; Eric Roberts 001; Paolo Rocchi; et al. (Informatics Curricula and Teaching Methods, 2002)

Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller. - Fernanda Gusmão de Lima Kastensmidt; Luigi Carro; Raoul Velazco; Ricardo Augusto da Luz Reis (IOLTW, 2002)

Injecting Multiple Upsets in a SEU tolerant 8051 Micro-controller. - Fernanda Lima 001; Luigi Carro; Raul Velazco; Ricardo Reis 001 (LATW, 2002)

A Comparison Between Testability Measures Applied to Complex Gates. - José Luís Güntzel; Gustavo Wilke; Márcio Bystronski; Ana Cristina Medina Pinto; Ricardo Reis 001 (LATW, 2002)

Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy. - Renato Fernandes Hentschke; Felipe S. Marques 001; Fernanda Lima 001; Luigi Carro; Altamiro Amadeu Susin; Ricardo Reis 001 (SBCCI, 2002)

A LEGAL Algorithm Following Global Routing. - Marcelo de Oliveira Johann; Glauco Borges Valim dos Santos; Ricardo Augusto da Luz Reis (SBCCI, 2002)

An IP of an Advanced Encryption Standard for Altera" Devices. - Alex Panato; Marcelo Barcelos; Ricardo Reis 001 (SBCCI, 2002)

Collaborative Design Using a Shared Object Spaces Infrastructure. - Sandro Sawicki; Lisane B. de Brisolara; Leandro S. lndrusiak; Ricardo Reis 001 (SBCCI, 2002)

Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path Tracing. - Gustavo Wilke; José Luís Güntzel; Márcio Bystronski; Ana Cristina Medina Pinto; Ricardo Reis 001 (SBCCI, 2002)

Designing fault tolerant systems into SRAM-based FPGAs. - Fernanda Lima 001; Luigi Carro; Ricardo Augusto da Luz Reis (DAC, 2003)

Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues. - Leandro Soares Indrusiak; Florian Lubitz; Ricardo Augusto da Luz Reis; Manfred Glesner (DATE, 2003)

A Low Device Occupation IP to Implement Rijndael Algorithm. - Alex Panato; Marcelo Barcelos; Ricardo Augusto da Luz Reis (DATE, 2003)

Supporting Consistency Control between Functional and Structural Views in Interface-based Design Models. - Leandro Soares Indrusiak; Ricardo Reis 001; Manfred Glesner (FDL, 2003)

Reducing pin and area overhead in fault-tolerant FPGA-based designs. - Fernanda Lima 001; Luigi Carro; Ricardo Augusto da Luz Reis (FPGA, 2003)

Plic-Plac: a novel constructive algorithm for placement. - Renato Fernandes Hentschke; Ricardo Reis 001 (ISCAS (5), 2003)

A Visual Simulation Tool at Layout Level. - Alexandre Casacurta; Marcel Furtado Almeida; Ricardo Augusto da Luz Reis (MSE, 2003)

Reducing Authoring Costs of Online Training in Microelectronics Design by Reusing Design Documentation Content. - Leandro Soares Indrusiak; Manfred Glesner; Ricardo Augusto da Luz Reis; Giuliana Alcántara; Stefan Hoermann 004; Ralf Steinmetz (MSE, 2003)

Power and Timing Driven Physical Design Automation. - Ricardo Augusto da Luz Reis (PATMOS, 2003)

Improving Critical Path Identification in Functional Timing Analysis. - Daniel Lima Ferrão; Gustavo Wilke; Ricardo Augusto da Luz Reis; José Luís Almada Güntzel (SBCCI, 2003)

Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations. - Renato Fernandes Hentschke; Ricardo Augusto da Luz Reis (SBCCI, 2003)

A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. - Cristiano Santos; Gustavo Wilke; Cristiano Lazzari; Ricardo Reis 001; José Luís Almada Güntzel (SBCCI, 2003)

A study on the performance of fast initial placement algorithms. - Renato Fernandes Hentschke; Marcelo de Oliveira Johann; Ricardo Augusto da Luz Reis (VLSI-SOC, 2003)

A New Macro-cell Generation Strategy for three metal layer CMOS Technologies. - Cristiano Lazzari; Cristiano Viana Domingues; José Luís Almada Güntzel; Ricardo Augusto da Luz Reis (VLSI-SOC, 2003)

A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits. - Cristiano Lazzari; Cristiano Viana Domingues; José Luís Güntzel; Ricardo Reis 001 (VLSI-SoC (Selected Papers), 2003)

Quadrature sampling schemes with improved image rejection. - Kong-Pang Pun; José E. da Franca; Carlos Azeredo Leme; Ricardo Reis 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

A multiple bit upset tolerant SRAM memory. - Gustavo Neuberger; Fernanda Gusmão de Lima Kastensmidt; Luigi Carro; Ricardo Augusto da Luz Reis (ACM Trans. Design Autom. Electr. Syst., 2003)

Designing and testing fault-tolerant techniques for SRAM-based FPGAs. - Fernanda Lima Kastensmidt; Gustavo Neuberger; Luigi Carro; Ricardo Reis 001 (Conf. Computing Frontiers, 2004)

Physical design methodologies for performance predictability and manufacturability. - Ricardo Reis 001; Fernanda Lima Kastensmidt; José Luís Almada Güntzel (Conf. Computing Frontiers, 2004)

Design of Very Deep Pipelined Multipliers for FPGAs. - Alex Panato; Sandro V. Silva; Flávio Rech Wagner; Marcelo O. Johann; Ricardo Reis 001; Sergio Bampi (DATE, 2004)

Requirements for Computer-Aided Learning from the Point of View of Electronic Design. - Ricardo Reis 001 (EDUTECH, 2004)

A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool. - Fabricio B. Bastian; Cristiano Lazzari; José Luís Almada Güntzel; Ricardo Reis 001 (PATMOS, 2004)

Accurate capture of timing parameters in inductively-coupled on-chip interconnects. - Tudor Murgan; Clemens Schlachta; Mihail Petrov; Leandro Soares Indrusiak; Alberto García Ortiz; Manfred Glesner; Ricardo A. L. Reis (SBCCI, 2004)

Lookup-based Remote Laboratory for FPGA Digital Design Prototyping. - Leandro Soares Indrusiak; Manfred Glesner; Ricardo Augusto da Luz Reis (VIRTUAL-LAB, 2004)

Designing Fault-Tolerant Techniques for SRAM-Based FPGAs. - Fernanda Lima Kastensmidt; Gustavo Neuberger; Renato Fernandes Hentschke; Luigi Carro; Ricardo Reis 001 (IEEE Des. Test Comput., 2004)

Um Framework de Apoio à Colaboração no Projeto Distribuído de Sistemas Integrados. - Leandro Soares Indrusiak; Ricardo A. L. Reis; Manfred Glesner (RITA, 2004)

Comparing high-level modeling approaches for embedded system design. - Lisane B. de Brisolara; Leandro Buss Becker; Luigi Carro; Flávio Rech Wagner; Carlos Eduardo Pereira; Ricardo Reis 001 (ASP-DAC, 2005)

TOC-BISR: A Self-Repair Scheme for Memories in Embedded Systems. - Gustavo Neuberger; Fernanda Lima Kastensmidt; Ricardo Reis 001 (IESS, 2005)

Blue Macaw: A Didactic Placement Tool Using Simulated Annealing. - Renato Fernandes Hentschke; Marcelo O. Johann; Ricardo Reis 001 (EDUTECH, 2005)

On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study. - Cristiano Lazzari; Lorena Anghel; Ricardo A. L. Reis (IOLTS, 2005)

Incremental timing optimization for automatic layout generation. - Cristiano Santos; Daniel Lima Ferrão; Ricardo Reis 001; José Luís Güntzel (ISCAS (4), 2005)

Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory. - Rodrigo Possamai Bastos; Fernanda Lima Kastensmidt; Ricardo Reis 001 (PATMOS, 2005)

Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation. - José Carlos S. Palma; César A. M. Marcon; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Ricardo A. L. Reis; Altamiro Amadeu Susin (SBCCI, 2005)

A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming. - Cristiano Lazzari; Lorena Anghel; Ricardo Reis 001 (VLSI-SoC, 2005)

Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. - César A. M. Marcon; José Carlos S. Palma; Ney Laert Vilar Calazans; Fernando Gehm Moraes; Altamiro Amadeu Susin; Ricardo Augusto da Luz Reis (VLSI-SoC, 2005)

A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. - Leonardo Londero de Oliveira; Cristiano Santos; Daniel Lima Ferrão; Eduardo A. C. da Costa; José Monteiro 001; João Baptista dos Santos Martins; Sergio Bampi; Ricardo Augusto da Luz Reis (VLSI-SoC, 2005)

An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories. - Gustavo Neuberger; Fernanda Gusmão de Lima Kastensmidt; Ricardo Reis 001 (IEEE Des. Test Comput., 2005)

Desenvolvimento de Técnicas de Tolerância à Falhas para Componentes Programáveis por SRAM. - Fernanda Lima Kastensmidt; Gustavo Neuberger; Luigi Carro; Ricardo Reis 001 (RITA, 2005)

A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits. - Cristiano Lazzari; Cristiano Santos; Ricardo Reis 001 (ICECS, 2006)

Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits. - Sandro Sawicki; Renato Fernandes Hentschke; Marcelo O. Johann; Ricardo Reis 001 (ICECS, 2006)

orBDDs Direct Mapping for Structured Logic Circuits. - Reginaldo Tavares; Cristina Meinhardt; Ricardo Reis 001 (ICECS, 2006)

Design of a Robust 8-Bit Microprocessor to Soft Errors. - Rodrigo Possamai Bastos; Fernanda Lima Kastensmidt; Ricardo Reis 001 (IOLTS, 2006)

Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study. - Cristiano Lazzari; Ricardo A. L. Reis; Lorena Anghel (IOLTS, 2006)

Channel based routing in channel-less circuits. - Glauco Borges Valim dos Santos; Marcelo de Oliveira Johann; Ricardo Augusto da Luz Reis (ISCAS, 2006)

A Regular Layout Approach for ASICs. - Claudio Menezes; Cristina Meinhardt; Ricardo Reis 001; Reginaldo Tavares (ISVLSI, 2006)

Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip. - José Carlos S. Palma; Ricardo A. L. Reis; Leandro Soares Indrusiak; Alberto García Ortiz; Manfred Glesner; Fernando Gehm Moraes (ISVLSI, 2006)

Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis. - Daniel Lima Ferrão; Ricardo Reis 001; José Luís Almada Güntzel (PATMOS, 2006)

Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry. - José Carlos S. Palma; Leandro Soares Indrusiak; Fernando Gehm Moraes; Alberto García Ortiz; Manfred Glesner; Ricardo A. L. Reis (PATMOS, 2006)

Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates. - Rodrigo Possamai Bastos; Fernanda Lima Kastensmidt; Ricardo Reis 001 (SBCCI, 2006)

Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing. - Renato Fernandes Hentschke; Guilherme Flach; Felipe Pinto; Ricardo Reis 001 (SBCCI, 2006)

An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias. - Renato Fernandes Hentschke; Sandro Sawicki; Marcelo O. Johann; Ricardo Augusto da Luz Reis (VLSI-SoC, 2006)

A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits. - Renato Fernandes Hentschke; Sandro Sawicki; Marcelo O. Johann; Ricardo Reis 001 (VLSI-SoC (Selected Papers), 2006)

Logic and Physical Synthesis of Cell Arrays. - Cristina Meinhardt; Ricardo Reis 001; Reginaldo Tavares (ICECS, 2007)

Reducing the Power Consumption in Networks-on-Chip through Data Coding Schemes. - José Carlos S. Palma; Leandro Soares Indrusiak; Fernando Gehm Moraes; Ricardo Reis 001; Manfred Glesner (ICECS, 2007)

A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length. - Renato Fernandes Hentschke; Ricardo Reis 001 (ISCAS, 2007)

Maze routing steiner trees with effective critical sink optimization. - Renato Fernandes Hentschke; Jaganathan Narasimham; Marcelo O. Johann; Ricardo Augusto da Luz Reis (ISPD, 2007)

Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations. - Lucas Brusamarello; Roberto da Silva; Ricardo A. L. Reis; Gilson I. Wirth (ISVLSI, 2007)

3D-Vias Aware Quadratic Placement for 3D VLSI Circuits. - Renato Fernandes Hentschke; Guilherme Flach; Felipe Pinto; Ricardo Reis 001 (ISVLSI, 2007)

Inserting Data Encoding Techniques into NoC-Based Systems. - José Carlos S. Palma; Leandro Soares Indrusiak; Fernando Gehm Moraes; Alberto García Ortiz; Manfred Glesner; Ricardo A. L. Reis (ISVLSI, 2007)

A CAL Tool to Aid the Understanding of Logic Synthesis. - Reginaldo Tavares; William Lautenschlager; Ricardo Reis 001 (MSE, 2007)

An Educational Tool for Design Automation of CMOS Cells. - Adriel Ziesemer; Cristiano Lazzari; Ricardo Reis 001 (MSE, 2007)

Cell placement on graphics processing units. - Guilherme Flach; Marcelo O. Johann; Renato Fernandes Hentschke; Ricardo Reis 001 (SBCCI, 2007)

Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC. - Lisane B. de Brisolara; Sang-Il Han; Xavier Guerin; Luigi Carro; Ricardo Reis 001; Soo-Ik Chae; Ahmed Amine Jerraya (SCOPES, 2007)

Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level. - Lucas Brusamarello; Roberto da Silva; Gilson I. Wirth; Ricardo A. L. Reis (VLSI-SoC, 2007)

Statistical and Numerical Approach for a Computer efficient circuit yield analysis. - Lucas Brusamarello; Roberto da Silva; Gilson I. Wirth; Ricardo Reis 001 (VLSI-SoC (Selected Papers), 2007)

Efficient timing closure with a transistor level design flow. - Cristiano Lazzari; Cristiano Santos; Adriel Ziesemer; Lorena Anghel; Ricardo Reis 001 (VLSI-SoC, 2007)

Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies. - Gustavo Neuberger; Fernanda Gusmão de Lima Kastensmidt; Ricardo Reis 001; Gilson I. Wirth; Ralf Brederlow; Christian Pacha (VLSI-SoC, 2007)

Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies. - Gustavo Neuberger; Gilson I. Wirth; Fernanda Gusmão de Lima Kastensmidt; Ricardo Reis 001 (VLSI-SoC (Selected Papers), 2007)

Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC. - Sang-Il Han; Soo-Ik Chae; Lisane B. de Brisolara; Luigi Carro; Ricardo Reis 001; Xavier Guerin; Ahmed Amine Jerraya (Des. Autom. Embed. Syst., 2007)

A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis. - Cristiano Lazzari; Ricardo A. L. Reis; Lorena Anghel (J. Electron. Test., 2007)

Técnicas probabilísticas para análise de yield em nível elétrico usando propagação de erros e derivadas numéricas. - Lucas Brusamarello; Roberto da Silva; Gilson I. Wirth; Ricardo Augusto da Luz Reis (RITA, 2007)

On the Evolution of Remote Laboratories for Prototyping Digital Electronic Systems. - Leandro Soares Indrusiak; Manfred Glesner; Ricardo Reis 001 (IEEE Trans. Ind. Electron., 2007)

Design procedure for DVB-T receivers large tuning range LP filter. - Pasquale Delizia; Marcello De Matteis; Stefano D'Amico; Andrea Baschirotto; Carlos Azeredo Leme; Ricardo Reis 001 (ISCAS, 2008)

A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction. - Gustavo Wilke; Ricardo Reis 001 (ISVLSI, 2008)

A novel scheme to reduce short-circuit power in mesh-based clock architectures. - Gustavo Wilke; Renan Fonseca; Cecilia Mezzomo; Ricardo Reis 001 (SBCCI, 2008)

Probabilistic Approach for Yield Analysis of Dynamic Logic Circuits. - Lucas Brusamarello; Roberto da Silva; Gilson I. Wirth; Ricardo A. L. Reis (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips. - Matteo Sonza Reorda; Massimo Violante; Cristina Meinhardt; Ricardo Reis 001 (DATE, 2009)

An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs. - Matteo Sonza Reorda; Massimo Violante; Cristina Meinhardt; Ricardo Reis 001 (DFT, 2009)

An automated design methodology for layout generation targeting power leakage minimization. - Cristiano Lazzari; Adriel Ziesemer; Ricardo Reis 001 (ICECS, 2009)

On the accuracy of Elmore-based Delay Models. - Glauco B. V. dos Santos; Tiago Reimann; Marcelo de Oliveira Johann; Ricardo Augusto da Luz Reis (ICECS, 2009)

A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits. - Sandro Sawicki; Gustavo Wilke; Marcelo O. Johann; Ricardo Reis 001 (ICECS, 2009)

Comparing transient-fault effects on synchronous and on asynchronous circuits. - Rodrigo Possamai Bastos; Yannick Monnet; Gilles Sicard; Fernanda Lima Kastensmidt; Marc Renaudin; Ricardo Reis 001 (IOLTS, 2009)

Built-in aging monitoring for safety-critical applications. - Julio César Vázquez; Víctor H. Champac; Adriel Ziesemer; Ricardo Reis 001; Isabel C. Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (IOLTS, 2009)

Measuring the effectiveness of symmetric and asymmetric transistor sizing for Single Event Transient mitigation in CMOS 90nm technologies. - Thiago Assis; Fernanda Lima Kastensmidt; Gilson I. Wirth; Ricardo Reis 001 (LATW, 2009)

Recovery scheme for hardening system on programmable chips. - Cristina Meinhardt; Ricardo Reis 001; Massimo Violante; Matteo Sonza Reorda (LATW, 2009)

Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates. - Sidinei Ghissoni; João Baptista dos Santos Martins; Ricardo Augusto da Luz Reis; José C. Monteiro 001 (PATMOS, 2009)

Resource-and-time-aware test strategy for configurable quaternary logic blocks. - Érika F. Cota; Luigi Carro; Felipe Pinto; Ricardo Augusto da Luz Reis; Marcelo Lubaszewski (SBCCI, 2009)

Protecting digital circuits against hold time violation due to process variability. - Gustavo Neuberger; Gilson I. Wirth; Ricardo Reis 001 (SBCCI, 2009)

Challenges and Emerging Technologies for System Integration beyond the End of the Roadmap of Nano-CMOS. - Sergio Bampi; Ricardo Reis 001 (VLSI-SoC, 2009)

Design of a soft-error robust microprocessor. - Rodrigo Possamai Bastos; Fernanda Lima Kastensmidt; Ricardo Reis 001 (Microelectron. J., 2009)

Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff. - Renato Fernandes Hentschke; Jagannathan Narasimhan; Marcelo O. Johann; Ricardo Reis 001 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Non-uniform clock mesh optimization with linear programming buffer insertion. - Matthew R. Guthaus; Gustavo Wilke; Ricardo Reis 001 (DAC, 2010)

The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms. - Glauco Borges Valim dos Santos; Tiago Reimann; Marcelo O. Johann; Ricardo Reis 001 (ICCD, 2010)

Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. - Sidinei Ghissoni; Eduardo Costa 001; Cristiano Lazzari; José Monteiro 001; Levent Aksoy; Ricardo Reis 001 (ICECS, 2010)

A study on layout quality of automatic generated cells. - Gracieli Posser; Adriel Ziesemer; Daniel Guimares Jr.; Gustavo Wilke; Ricardo A. L. Reis (ICECS, 2010)

Routing algorithms performance in different routing scopes. - Tiago Reimann; Glauco B. V. dos Santos; Ricardo A. L. Reis (ICECS, 2010)

Design and verification of a layer-2 Ethernet MAC classification engine for a Gigabit Ethernet switch. - Jorge L. Tonfat; Ricardo Reis 001 (ICECS, 2010)

Evaluating transient-fault effects on traditional C-element's implementations. - Rodrigo Possamai Bastos; Gilles Sicard; Fernanda Lima Kastensmidt; Marc Renaudin; Ricardo Reis 001 (IOLTS, 2010)

Predictive error detection by on-line aging monitoring. - Julio César Vázquez; Víctor H. Champac; Adriel Ziesemer; Ricardo Reis 001; Jorge Semião; Isabel C. Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (IOLTS, 2010)

A Mesh-Buffer Displacement Optimization Strategy. - Guilherme Flach; Gustavo Wilke; Marcelo O. Johann; Ricardo Reis 001 (ISVLSI, 2010)

Logical Core Algorithm: Improving Global Placement. - Felipe Pinto; Lucas Cavalheiro; Marcelo O. Johann; Ricardo Reis 001 (ISVLSI, 2010)

Variability-aware physical design techniques. - Gustavo Wilke; Ricardo Reis 001 (LATW, 2010)

Low-sensitivity to process variations aging sensor for automotive safety-critical applications. - Julio César Vázquez; Víctor H. Champac; Adriel Ziesemer; Ricardo Reis 001; Isabel Maria Cacho Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (VTS, 2010)

3D-Via Driven Partitioning for 3D VLSI Integrated Circuits. - Sandro Sawicki; Gustavo Wilke; Marcelo O. Johann; Ricardo Reis 001 (CLEI Electron. J., 2010)

Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies. - Rodrigo Possamai Bastos; Gilles Sicard; Fernanda Lima Kastensmidt; Marc Renaudin; Ricardo Reis 001 (Microelectron. Reliab., 2010)

Design Tools and Methods for Chip Physical Design. - Ricardo Reis 001 (Multiprocessor System-on-Chip, 2011)

Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization. - Sidinei Ghissoni; Eduardo Costa 001; José Monteiro 001; Ricardo Reis 001 (ICECS, 2011)

Power consumption in transistor networks versus in standard cells. - Gerson Scartezzini; Ricardo Reis 001 (ICECS, 2011)

Design automation of transistor networks, a new challenge. - Ricardo Reis 001 (ISCAS, 2011)

Gate Sizing Minimizing Delay and Area. - Gracieli Posser; Guilherme Flach; Gustavo Wilke; Ricardo Reis 001 (ISVLSI, 2011)

Functional verification of logic modules for a Gigabit Ethernet switch. - Jorge L. Tonfat; Gustavo Neuberger; Ricardo Reis 001 (LATW, 2011)

Quadratic placement with single-iteration linear system solver. - Guilherme Flach; Marcelo O. Johann; Ricardo Reis 001 (SBCCI, 2011)

A Low-Cost Solution for Deploying Processor Cores in Harsh Environments. - Massimo Violante; Cristina Meinhardt; Ricardo Reis 001; Matteo Sonza Reorda (IEEE Trans. Ind. Electron., 2011)

Efficient area and power multiplication part of FFT based on twiddle factor decomposition. - Sidinei Ghissoni; Eduardo Costa 001; José Monteiro 001; Ricardo Reis 001 (ICECS, 2012)

Soft-Error Probability Due to SET in Clock Tree Networks. - Raul Chipana; Eduardo Chielle; Fernanda Lima Kastensmidt; Jorge L. Tonfat; Ricardo Reis 001 (ISVLSI, 2012)

Simulation of SET faults in a voltage controlled oscillator. - Walter E. Calienes Bartra; Fernanda Lima Kastensmidt; Ricardo Reis 001 (LATW, 2012)

SET susceptibility estimation of clock tree networks from layout extraction. - Raul Chipana; Fernanda Lima Kastensmidt; Jorge L. Tonfat; Ricardo Reis 001 (LATW, 2012)

Transistor sizing and gate sizing using geometric programming considering delay minimization. - Gracieli Posser; Guilherme Flach; Gustavo Wilke; Ricardo Reis 001 (NEWCAS, 2012)

Multi-bit flip-flop usage impact on physical synthesis. - Cristiano Santos; Ricardo Reis 001; Guilherme Godoi; Marcos Barros; Fabio Duarte (SBCCI, 2012)

Posicionamento de Circuitos 3D Considerando o Planejamento de 3D-Vias. - Renato Fernandes Hentschke; Marcelo O. Johann; Ricardo Reis 001 (RITA, 2012)

High-performance clock mesh optimization. - Matthew R. Guthaus; Xuchu Hu; Gustavo Wilke; Guilherme Flach; Ricardo Reis 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit. - Cristiano Santos; Pascal Vivet; Denis Dutoit; Philippe Garrault; Nicolas Peltier; Ricardo Reis 001 (3DIC, 2013)

Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip. - Anelise Kologeski; Caroline Concatto; Debora Matos; Daniel Grehs; Tiago Motta; Felipe Almeida; Fernanda Lima Kastensmidt; Altamiro Amadeu Susin; Ricardo Reis 001 (ICECS, 2013)

Instruction-driven timing CPU model for efficient embedded software development using OVP. - Felipe Rosa 001; Luciano Ost; Ricardo Reis 001; Gilles Sassatelli (ICECS, 2013)

A novel approach to reduce power consumption in level shifter for Multiple Dynamic Supply Voltage. - Marco Terres; Cristina Meinhardt; Guilherme Bontorin; Ricardo Reis 001 (ICECS, 2013)

Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing. - Tiago Reimann; Gracieli Posser; Guilherme Flach; Marcelo O. Johann; Ricardo Reis 001 (ISCAS, 2013)

Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities. - Guilherme Flach; Tiago Reimann; Gracieli Posser; Marcelo O. Johann; Ricardo Reis 001 (ISVLSI, 2013)

Message from the general and program chairs. - Fernanda Lima Kastensmidt; Ricardo Reis 001; Leandro Soares Indrusiak; Gilles Sassatelli (ISVLSI, 2013)

A yield-driven regular layout synthesis. - Cristina Meinhardt; Ricardo Reis 001 (ISVLSI, 2013)

Using electromagnetic emanations for variability characterization in Flash-based FPGAs. - Jimmy Tarrillo; Jorge L. Tonfat; Fernanda Lima Kastensmidt; Ricardo Reis 001; Florent Bruguier; Morgan Bourree; Pascal Benoit; Lionel Torres (ISVLSI, 2013)

FinFET basic cells evaluation for regular layouts. - Cristina Meinhardt; Ricardo Reis 001 (LASCAS, 2013)

Global routing congestion reduction with cost allocation look-ahead. - Leandro Nunes; Ricardo Reis 001 (SBCCI, 2013)

GR-PA: A cost pre-allocation model for global routing. - Leandro Nunes; Tiago Reimann; Ricardo Reis 001 (VLSI-SoC, 2013)

Revisiting automated physical synthesis of high-performance clock networks. - Matthew R. Guthaus; Gustavo Wilke; Ricardo Reis 001 (ACM Trans. Design Autom. Electr. Syst., 2013)

Using TSVs for thermal mitigation in 3D circuits: Wish and truth. - Cristiano Santos; Papa Momar Souare; François de Crecy; Perceval Coudrain; Jean-Philippe Colonna; Pascal Vivet; Andras Borbely; Ricardo Reis 001; M. Haykel Ben Jamaa; Vincent Fiori; Alexis Farcy (3DIC, 2014)

Thermal performance of 3D ICs: Analysis and alternatives. - Cristiano Santos; Pascal Vivet; Jean-Philippe Colonna; Perceval Coudrain; Ricardo Augusto da Luz Reis (3DIC, 2014)

Thermal modeling methodology for efficient system-level thermal analysis. - Cristiano Santos; Pascal Vivet; Gene Matter; Nicolas Peltier; Sylvian Kaiser; Ricardo Augusto da Luz Reis (CICC, 2014)

Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs. - Fernanda Lima Kastensmidt; Jorge L. Tonfat; Thiago Hanna Both; Paolo Rech; Gilson I. Wirth; Ricardo Reis 001; Florent Bruguier; Pascal Benoit; Lionel Torres; Christopher Frost 002 (ETS, 2014)

A design flow for physical synthesis of digital cells with ASTRAN. - Adriel Ziesemer; Ricardo Reis 001; Matheus T. Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans (ACM Great Lakes Symposium on VLSI, 2014)

A set of Virtual Instruments to simulate radiation effects in CMOS circuits. - Walter E. Calienes Bartra; Ricardo Reis 001 (I2MTC, 2014)

A tool to simulate optical lithography in nanoCMOs. - Tania Mara Ferla; Guilherme Flach; Ricardo Reis 001 (I2MTC, 2014)

A systematic approach for analyzing and optimizing cell-internal signal electromigration. - Gracieli Posser; Vivek Mishra; Palkesh Jain; Ricardo Reis 001; Sachin S. Sapatnekar (ICCAD, 2014)

Impact of gate workfunction fluctuation on FinFET standard cells. - Cristina Meinhardt; Alexandra L. Zimpeck; Ricardo Augusto da Luz Reis (ICECS, 2014)

Analyzing the electromigration effects on different metal layers and different wire lengths. - Gracieli Posser; Vivek Mishra; Ricardo Augusto da Luz Reis; Sachin S. Sapatnekar (ICECS, 2014)

Thermal impact of 3D stacking and die thickness: Analysis and characterization of a memory-on-logic 3D circuit. - Cristiano Santos; Pascal Vivet; Ricardo Augusto da Luz Reis (ICECS, 2014)

Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices. - Gracieli Posser; Jozeanne Belomo; Cristina Meinhardt; Ricardo Augusto da Luz Reis (ISVLSI, 2014)

Simultaneous Two-Dimensional Cell Layout Compaction Using MILP with ASTRAN. - Adriel Mota Ziesemer; Ricardo Augusto da Luz Reis (ISVLSI, 2014)

Comparing high-performance cells in CMOS bulk and FinFET technologies. - Cristina Meinhardt; Ricardo Reis 001 (LASCAS, 2014)

Exploring more efficient architectures for Multiple Dynamic Supply Voltage designs. - Marco Terres; Cristina Meinhardt; Guilherme Bontorin; Ricardo Reis 001 (LASCAS, 2014)

Automatic layout synthesis with ASTRAN applied to asynchronous cells. - Adriel Ziesemer; Ricardo Reis 001; Matheus T. Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans (LASCAS, 2014)

Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects. - Lucas A. Tambara; Jorge L. Tonfat; Ricardo Reis 001; Fernanda Lima Kastensmidt; Evaldo Carlos Fonseca Pereira; Rafael Galhardo Vaz; Odair Lelis Goncalez (LATW, 2014)

Bulk and FDSOI SRAM resiliency to radiation effects. - Walter E. Calienes Bartra; Ricardo Augusto da Luz Reis; Costin Anghel; Andrei Vladimirescu (MWSCAS, 2014)

Fast energy evaluation of embedded applications for many-core systems. - Felipe Rosa 001; Luciano Ost; Thiago Raupp da Rosa; Fernando Gehm Moraes; Ricardo Reis 001 (PATMOS, 2014)

Evaluating the impact of environment and physical variability on the ION current of 20nm FinFET devices. - Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Reis 001 (PATMOS, 2014)

Automated Synthesis of Cell Libraries for Asynchronous Circuits. - Matheus Trevisan; Michel Evandro Arendt; Adriel Ziesemer; Ricardo Augusto da Luz Reis; Ney Laert Vilar Calazans (SBCCI, 2014)

Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity. - Giovanni Bruni; Paolo Rech; Lucas A. Tambara; Gabriel L. Nazar; Fernanda Gusmão de Lima Kastensmidt; Ricardo Reis 001; Alessandro Paccagnella (VLSI-SoC, 2014)

Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs. - Fernanda Lima Kastensmidt; Jorge L. Tonfat; Thiago Hanna Both; Paolo Rech; Gilson I. Wirth; Ricardo Reis 001; Florent Bruguier; Pascal Benoit; Lionel Torres; Christopher Frost 002 (Microelectron. Reliab., 2014)

Predictive evaluation of electrical characteristics of sub-22 nm FinFET technologies under device geometry variations. - Cristina Meinhardt; Alexandra L. Zimpeck; Ricardo A. L. Reis (Microelectron. Reliab., 2014)

Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation. - Guilherme Flach; Tiago Reimann; Gracieli Posser; Marcelo O. Johann; Ricardo Reis 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Graphite-based heat spreaders for hotspot mitigation in 3D ICs. - Cristiano Santos; Rafael Prieto; Pascal Vivet; Jean-Philippe Colonna; Perceval Coudrain; Ricardo Reis 001 (3DIC, 2015)

Energy efficient frame-level redundancy scrubbing technique for SRAM-based FPGAs. - Jorge L. Tonfat; Fernanda Lima Kastensmidt; Ricardo Reis 001 (AHS, 2015)

Gate sizing and threshold voltage assignment for high performance microprocessor designs. - Tiago Reimann; Cliff C. N. Sze; Ricardo Reis 001 (ASP-DAC, 2015)

A fast and scalable fault injection framework to evaluate multi/many-core soft error reliability. - Felipe Rosa 001; Fernanda Lima Kastensmidt; Ricardo Reis 001; Luciano Ost (DFTS, 2015)

Bulk and FDSOI Sub-micron CMOS transistors resilience to single-event transients. - Walter E. Calienes Bartra; Andrei Vladimirescu; Ricardo Reis 001 (ICECS, 2015)

Impact on performance, power, area and wirelength using electromigration-aware cells. - Gracieli Posser; Vivek Mishra; Palkesh Jain; Ricardo Reis 001; Sachin S. Sapatnekar (ICECS, 2015)

Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability. - Felipe Rosa 001; Raphael Martins Brum; Gilson I. Wirth; Luciano Ost; Ricardo Reis 001 (ICECS, 2015)

Process variability in FinFET standard cells with different transistor sizing techniques. - Alexandra L. Zimpeck; Cristina Meinhardt; Gracieli Posser; Ricardo Reis 001 (ICECS, 2015)

Low Latency FPGA Implementation of Izhikevich-Neuron Model. - Vitor V. Bandeira; Vivianne L. Costa; Guilherme Bontorin; Ricardo A. L. Reis (IESS, 2015)

A mixed cells physical design approach. - Daniel S. Guimarães Jr.; Julia Casarin Puget; Ricardo Augusto da Luz Reis (ISCAS, 2015)

Analyzing the Impact of Frequency and Diverse Path Delays in the Time Vulnerability Factor of Master-Slave D Flip-Flops. - Alexandra L. Zimpeck; Fernanda Lima Kastensmidt; Ricardo Reis 001 (ISVLSI, 2015)

Modeling the impact of heavy ion on FDSOI NanoCMOS. - Walter E. Calienes Bartra; Ricardo Reis 001; Andrei Vladimirescu (LASCAS, 2015)

Efficient emulation of quantum circuits on classical hardware. - Calebe Conceição; Ricardo Reis 001 (LASCAS, 2015)

Reducing the signal Electromigration effects on different logic gates by cell layout optimization. - Gracieli Posser; Lucas de Paris; Vivek Mishra; Palkesh Jain; Ricardo Reis 001; Sachin S. Sapatnekar (LASCAS, 2015)

Overhead for independent net approach for Global Routing. - Diego Tumelero; Guilherme Bontorin; Ricardo Reis 001 (LASCAS, 2015)

Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments. - Jimmy Tarrillo; Jorge L. Tonfat; Lucas A. Tambara; Fernanda Lima Kastensmidt; Ricardo Reis 001 (LATS, 2015)

Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs. - Sidinei Ghissoni; Eduardo Costa 001; Ricardo Reis 001 (PATMOS, 2015)

Energy-efficient Level Shifter topology. - Roger Caputo-Llanos; Diego Sousa; Marco Terres; Guilherme Bontorin; Ricardo Reis 001; Marcelo O. Johann (PATMOS, 2015)

Jezz: An Effective Legalization Algorithm for Minimum Displacement. - Julia Casarin Puget; Guilherme Flach; Marcelo O. Johann; Ricardo Augusto da Luz Reis (SBCCI, 2015)

An Incremental Timing-Driven flow using quadratic formulation for detailed placement. - Guilherme Flach; Jucemar Monteiro; Mateus Fogaça; Julia Casarin Puget; Paulo F. Butzen; Marcelo O. Johann; Ricardo Augusto da Luz Reis (VLSI-SoC, 2015)

Impact of dynamic voltage scaling and thermal factors on SRAM reliability. - Felipe Rosa 001; Raphael Martins Brum; Gilson I. Wirth; Fernanda Gusmão de Lima Kastensmidt; Luciano Ost; Ricardo Reis 001 (Microelectron. Reliab., 2015)

Impact of PVT variability on 20 nm FinFET standard cells. - Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Augusto da Luz Reis (Microelectron. Reliab., 2015)

Extending FreeRTOS to support dynamic and distributed mapping in multiprocessor systems. - Geancarlo Abich; Marcelo G. Mandelli; Felipe R. Rosa 001; Fernando Gehm Moraes; Luciano Ost; Ricardo Reis 001 (ICECS, 2016)

Quadratic timing objectives for incremental timing-driven placement optimization. - Mateus Fogaça; Guilherme Flach; Jucemar Monteiro; Marcelo O. Johann; Ricardo Reis 001 (ICECS, 2016)

DHyANA: A NoC-based neural network hardware architecture. - Priscila C. Holanda; Cezar R. W. Reinbrecht; Guilherme Bontorin; Vitor V. Bandeira; Ricardo A. L. Reis (ICECS, 2016)

Geometric variability impact on 7nm Trigate combinational cells. - Alexandra L. Zimpeck; Ygor Aguiar; Cristina Meinhardt; Ricardo Reis 001 (ICECS, 2016)

Impact of variability effects on FinFET transistors and combinational cells. - Alexandra L. Zimpeck; Ricardo Reis 001 (ICECS, 2016)

Electromigration aware circuits by using special signal non-default routing rules. - Lucas de Paris; Gracieli Posser; Ricardo Reis 001 (ISCAS, 2016)

FinFET cells with different transistor sizing techniques against PVT variations. - Alexandra L. Zimpeck; Cristina Meinhardt; Gracieli Posser; Ricardo Augusto da Luz Reis (ISCAS, 2016)

Drive Strength Aware Cell Movement Techniques for Timing Driven Placement. - Guilherme Flach; Mateus Fogaça; Jucemar Monteiro; Marcelo O. Johann; Ricardo Augusto da Luz Reis (ISPD, 2016)

Cell Selection for High-Performance Designs in an Industrial Design Flow. - Tiago J. Reimann; Cliff C. N. Sze; Ricardo Reis 001 (ISPD, 2016)

Routing-Aware Incremental Timing-Driven Placement. - Jucemar Monteiro; Nima Karimpour Darav; Guilherme Flach; Mateus Fogaça; Ricardo Augusto da Luz Reis; Andrew A. Kennings; Marcelo O. Johann; Laleh Behjat (ISVLSI, 2016)

Reducing the number of transistors with gate clustering. - Calebe Conceição; Gracieli Posser; Ricardo Reis 001 (LASCAS, 2016)

Improving placement algorithms by using visualization tools. - Mateus Fogaça; Guilherme Flach; Marcelo O. Johann; Ricardo Augusto da Luz Reis (NEWCAS, 2016)

Leakage current analysis in static CMOS logic gates for a transistor network design approach. - Jorge L. Tonfat; Guilherme Flach; Ricardo Reis 001 (PATMOS, 2016)

Challenges of cell selection algorithms in industrial high performance microprocessor designs. - Tiago Reimann; Cliff C. N. Sze; Ricardo Reis 001 (Integr., 2016)

Selected Articles from the 6th International Workshop on CMOS Variability, Salvador, Bahia, Brazil, September 1-4, 2015. - Ricardo Reis 001; Nadine Azémard (J. Low Power Electron., 2016)

Permanent and single event transient faults reliability evaluation EDA tool. - Y. Q. de Aguiar; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Augusto da Luz Reis (Microelectron. Reliab., 2016)

FDSOI and Bulk CMOS SRAM Cell Resilience to Radiation Effects. - Walter E. Calienes Bartra; Andrei Vladimirescu; Ricardo Augusto da Luz Reis (Microelectron. Reliab., 2016)

Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization. - Gracieli Posser; Vivek Mishra; Palkesh Jain; Ricardo Reis 001; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

SET response of FinFET-based majority voter circuits under work-function fluctuation. - Y. Q. de Aguiar; Fernanda Lima Kastensmidt; Cristina Meinhardt; Ricardo A. L. Reis (ICECS, 2017)

Temperature dependence and ZTC bias point evaluation of sub 20nm bulk multigate devices. - Ygor Q. Aguiar; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo A. L. Reis (ICECS, 2017)

A cell clustering technique to reduce transistor count. - Calebe Conceição; Gisell Moura; Filipe Pisoni; Ricardo Reis 001 (ICECS, 2017)

UFRGSPlace: Routability driven FPGA placement algorithm for heterogeneous FPGAs. - Julia Casarin Puget; Andre Saldanha Oliveira; Jorge Seelen; Ricardo Reis 001 (ICECS, 2017)

Investigating parallel TMR approaches and thread disposability in Linux. - Gennaro Severino Rodrigues; Felipe Rosa 001; Fernanda Lima Kastensmidt; Ricardo Reis 001; Luciano Ost (ICECS, 2017)

Impact of schmitt trigger inverters on process variability robustness of 1-Bit full adders. - Samuel Presa Toledo; Alexandra L. Zimpeck; Ricardo Reis 001; Cristina Meinhardt (ICECS, 2017)

Publish-subscribe programming for a NoC-based multiprocessor system-on-chip. - Jean Carlo Hamerski; Geancarlo Abich; Ricardo Reis 001; Luciano Ost; Alexandre M. Amory (ISCAS, 2017)

Robustness of Sub-22nm multigate devices against physical variability. - Alexandra L. Zimpeck; Ygor Aguiar; Cristina Meinhardt; Ricardo Reis 001 (ISCAS, 2017)

Rsyn: An Extensible Physical Synthesis Framework. - Guilherme Flach; Mateus Fogaça; Jucemar Monteiro; Marcelo O. Johann; Ricardo Augusto da Luz Reis (ISPD, 2017)

Radiation sensitivity of XOR topologies in multigate technologies under voltage variability. - Ygor Q. de Aguiar; Cristina Meinhardt; Ricardo A. L. Reis (LASCAS, 2017)

Process and temperature impact on single-event transients in 28nm FDSOI CMOS. - Walter E. Calienes Bartra; Andrei Vladimirescu; Ricardo Reis 001 (LASCAS, 2017)

Evaluation of multicore systems soft error reliability using virtual platforms. - Felipe Rosa 001; Luciano Ost; Ricardo Reis 001; Simon Davidmann; Larry Lapides (NEWCAS, 2017)

VLSI-SoC: An Enduring Tradition. - Ricardo Reis 001; Manfred Glesner (VLSI-SoC (Selected Papers), 2017)

Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology. - Y. Q. de Aguiar; Laurent Artola; Guillaume Hubert; Cristina Meinhardt; Fernanda Lima Kastensmidt; Ricardo Augusto da Luz Reis (Microelectron. Reliab., 2017)

Evaluation of heavy-ion impact in bulk and FDSOI devices under ZTC condition. - Walter E. Calienes Bartra; Y. Q. de Aguiar; Cristina Meinhardt; Andrei Vladimirescu; Ricardo Augusto da Luz Reis (Microelectron. Reliab., 2017)

Extensive evaluation of programming models and ISAs impact on multicore soft error reliability. - Felipe da Rosa 001; Vitor V. Bandeira; Ricardo Reis 001; Luciano Ost (DAC, 2018)

Exploring Multi-level Design to Mitigate Variability and Radiation Effects on 7nm FinFET Logic Cells. - Leonardo Heitich Brendler; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Reis 001 (ICECS, 2018)

Impact of Near-Threshold and Variability on 7nm FinFET XOR Circuits. - Fabio G. Rossato G. da Silva; Cristina Meinhardt; Ricardo Reis 001 (ICECS, 2018)

Strategies for Reducing Power Consumption and Increasing Reliability in IoT. - Ricardo Reis 001 (IFIPIoT@WCC, 2018)

Exploring the Impact of Soft Errors on NoC-based Multiprocessor Systems. - Felipe T. Bortolon; Geancarlo Abich; Sergio Bampi; Ricardo Reis 001; Fernando Moraes 001; Luciano Ost (ISCAS, 2018)

Pros and Cons of Schmitt Trigger Inverters to Mitigate PVT Variability on Full Adders. - Samuel Presa Toledo; Alexandra L. Zimpeck; Ricardo Reis 001; Cristina Meinhardt (ISCAS, 2018)

An automated methodology to fix electromigration violations on a customized design flow. - Lucas de Paris; Ricardo Reis 001 (LASCAS, 2018)

A nonlinear placement for FPGAs: The chaotic place. - Elias de Almeida Ramos; Guilherme Bontorin; Ricardo Reis 001 (LASCAS, 2018)

gem5-FIM: a flexible and scalable multicore soft error assessment framework to early reliability design space explorations. - Felipe Rocha da Rosa 001; Ricardo Reis 001; Luciano Ost (LASCAS, 2018)

Reducing the amount of transistors by gate merging. - Luciana Mendes da Silva; Guilherme Bontorin; Ricardo Reis 001 (LASCAS, 2018)

A Design Patterns-Based Middleware for Multiprocessor Systems-on-Chip. - Jean Carlo Hamerski; Geancarlo Abich; Ricardo Reis 001; Luciano Ost; Alexandre M. Amory (SBCCI, 2018)

Evaluation of Compiler Optimization Flags Effects on Soft Error Resiliency. - Guilherme E. Medeiros; Felipe T. Bortolon; Ricardo Reis 001; Luciano Ost (SBCCI, 2018)

Evaluating the Impact of Process Variability and Radiation Effects on Different Transistor Arrangements. - Leonardo Heitich Brendler; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Reis 001 (VLSI-SoC, 2018)

Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies. - Roberto B. Almeida; Cleiton Magano Marques; Paulo F. Butzen; Fábio G. R. G. da Silva; Ricardo A. L. Reis; Cristina Meinhardt (Microelectron. Reliab., 2018)

Evaluation of variability using Schmitt trigger on full adders layout. - Leonardo B. Moraes; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Augusto da Luz Reis (Microelectron. Reliab., 2018)

Impact of different transistor arrangements on gate variability. - Alexandra L. Zimpeck; Cristina Meinhardt; Laurent Artola; Guillaume Hubert; Fernanda Lima Kastensmidt; Ricardo Augusto da Luz Reis (Microelectron. Reliab., 2018)

Finding placement-relevant clusters with fast modularity-based clustering. - Mateus Fogaça; Andrew B. Kahng; Ricardo Reis 001; Lutong Wang (ASP-DAC, 2019)

Proposal and Evaluation of Pin Access Algorithms for Detailed Routing. - Marcelo Danigno; Paulo F. Butzen; Jorge Ferreira; André Oliveira 003; Eder Monteiro; Mateus Fogaça; Ricardo Augusto da Luz Reis (ICECS, 2019)

FBM: A Simple and Fast Algorithm for Placement Legalization. - Jorge Ferreira; Paulo F. Butzen; Cristina Meinhardt; Ricardo A. L. Reis (ICECS, 2019)

FinFET Variability and Near-threshold operation: Impact on Full Adders design using XOR Blocks. - Fabio G. Rossato G. da Silva; Cristina Meinhardt; Ricardo Augusto da Luz Reis (ICECS, 2019)

Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility. - Alexandra L. Zimpeck; Cristina Meinhardt; Laurent Artola; Guillaume Hubert; Fernanda Lima Kastensmidt; Ricardo Augusto da Luz Reis (ICECS, 2019)

Challenges in the Design of Integrated Systems for IoT. - Ricardo Reis 001 (IFIPIoT, 2019)

Evaluation of Compilers Effects on OpenMP Soft Error Resiliency. - Jonas Gava; Vitor V. Bandeira; Ricardo Reis 001; Luciano Ost (ISVLSI, 2019)

Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm. - Henrique Placido; Ricardo Reis 001 (ISVLSI, 2019)

Clip Clustering for Early Lithographic Hotspot Classification. - Andre Saldanha Oliveira; Julia Casarin Puget; Carolina Metzler; Ricardo Reis 001 (LASCAS, 2019)

Process Variability Challenges for Radiation Mitigation Techniques on 16nm. - Samuel Presa Toledo; Ricardo Reis 001; Cristina Meinhardt (LASCAS, 2019)

Exploring Schmitt Trigger Circuits for Process Variability Mitigation. - Leonardo B. Moraes; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Augusto da Luz Reis (NEWCAS, 2019)

Cryptography by Synchronization of Hopfield Neural Networks that Simulate Chaotic Signals Generated by the Human Body. - Elias de Almeida Ramos; João Carlos Britto Filho; Ricardo A. L. Reis (NEWCAS, 2019)

Exploring area and total wirelength using a cell merging technique. - Kevin A. Cáceres Albinagorta; Calebe Conceição; Carlos Silva Cárdenas; Ricardo A. L. Reis (VLSI-SoC, 2019)

Soft Error Reliability Analysis of Autonomous Vehicles Software Stack. - Vitor V. Bandeira; Isadora Oliveira; Felipe da Rosa 001; Ricardo A. L. Reis; Luciano Ost (VLSI-SoC, 2019)

Efficient Soft Error Vulnerability Analysis Using Non-intrusive Fault Injection Techniques. - Vitor V. Bandeira; Felipe Rosa 001; Ricardo Reis 001; Luciano Ost (VLSI-SoC (Selected Papers), 2019)

Non-intrusive Fault Injection Techniques for Efficient Soft Error Vulnerability Analysis. - Vitor V. Bandeira; Felipe Rosa 001; Ricardo Augusto da Luz Reis; Luciano Ost (VLSI-SoC, 2019)

Process Variability Impact on the SET Response of FinFET Multi-level Design. - Leonardo Heitich Brendler; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Reis 001 (VLSI-SoC (Selected Papers), 2019)

Evaluation of SET under Process Variability on FinFET Multi-level Design. - Leonardo Heitich Brendler; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo A. L. Reis (VLSI-SoC, 2019)

Impact of Process Variability and Single Event Transient on FinFET Technology. - Leonardo Heitich Brendler; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo A. L. Reis (VLSI-SoC, 2019)

Netlist Optimization by Gate Merging. - Calebe Micael de Oliveira Conceição; Ricardo Augusto da Luz Reis (VLSI-SoC, 2019)

Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability. - Leonardo B. Moraes; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Augusto da Luz Reis (VLSI-SoC, 2019)

Robustness and Minimum Energy-Oriented FinFET Design. - Leonardo B. Moraes; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Augusto da Luz Reis (VLSI-SoC, 2019)

Robust FinFET Schmitt Trigger Designs for Low Power Applications. - Leonardo B. Moraes; Alexandra Lackmann Zimpeck; Cristina Meinhardt; Ricardo A. L. Reis (VLSI-SoC (Selected Papers), 2019)

Exploration of Techniques to Assess Soft Errors in Multicore Architectures. - Isadora Oliveira; Vitor V. Bandeira; Ricardo A. L. Reis; Luciano Ost (VLSI-SoC, 2019)

Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs. - Alexandra L. Zimpeck; Cristina Meinhardt; Laurent Artola; Guillaume Hubert; Fernanda Lima Kastensmidt; Ricardo Augusto da Luz Reis (VLSI-SoC, 2019)

Exploiting memory allocations in clusterised many-core architectures. - Rafael Garibotti; Luciano Ost; Anastasiia Butko; Ricardo Reis 001; Abdoulaye Gamatié; Gilles Sassatelli (IET Comput. Digit. Tech., 2019)

Transistor Count Reduction by Gate Merging. - Calebe Micael de Oliveira Conceição; Ricardo Augusto da Luz Reis (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A New Nonlinear Global Placement for FPGAs: The Chaotic Place. - Elias de Almeida Ramos; Guilherme Bontorin; Ricardo Reis 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Using Machine Learning Techniques to Evaluate Multicore Soft Error Reliability. - Felipe Rocha da Rosa 001; Rafael Garibotti; Luciano Ost; Ricardo Reis 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Soft Error Reliability Using Virtual Platforms - Early Evaluation of Multicore Systems - Felipe Rocha da Rosa 001; Luciano Ost; Ricardo Reis 001 (Springer, 2020)

Hardware Architecture for the Regular Interpolation Filter of the AV1 Video Coding Standard. - Daiane Freitas; Rafael da Silva; Ícaro Siqueira; Cláudio Machado Diniz; Ricardo A. L. Reis; Mateus Grellert (EUSIPCO, 2020)

Contributions to OpenROAD from Abroad: Experiences and Learnings : Invited Paper. - Mateus Fogaça; Eder Monteiro; Marcelo Danigno; Isadora Oliveira; Paulo F. Butzen; Ricardo Reis 001 (ICCAD, 2020)

Soft Error Reliability Assessment of Neural Networks on Resource-constrained IoT Devices. - Geancarlo Abich; Jonas Gava; Ricardo Reis 001; Luciano Ost (ICECS, 2020)

Mirror Full Adder SET Susceptibility on 7nm FinFET Technology. - Rafael N. M. Oliveira; Fábio G. R. G. da Silva; Ricardo Reis 001; Cristina Meinhardt (ICECS, 2020)

Pros and Cons of ST and SIG FinFET Inverters for Low Power Designs. - Leonardo B. Moraes; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Reis 001 (ISCAS, 2020)

Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits. - Juliano C. Zanelli; Carolina Metzler; Ricardo Augusto da Luz Reis (LASCAS, 2020)

Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters. - Leonardo Heitich Brendler; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Augusto da Luz Reis (LATS, 2020)

Circuit Level Design Methods to Mitigate Soft Errors. - Ricardo A. L. Reis; Cristina Meinhardt; Alexandra L. Zimpeck; Leonardo Heitich Brendler; Leonardo B. Moraes (LATS, 2020)

Mitigation Effects of Decoupling Cells on Full Adders Process Variability. - Fabio G. Rossato G. da Silva; Cristina Meinhardt; Ricardo Reis 001 (MWSCAS, 2020)

Fast and Scalable I/O Pin Assignment with Divide-and-Conquer and Hungarian Matching. - Vitor V. Bandeira; Mateus Fogaça; Eder Matheus Monteiro; Isadora Oliveira; Mingyu Woo; Ricardo Augusto da Luz Reis (NEWCAS, 2020)

RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique. - Jonas Gava; Ricardo Reis 001; Luciano Ost (VLSI-SoC (Selected Papers), 2020)

RAT: A Lightweight System-level Soft Error Mitigation Technique. - Jonas Gava; Ricardo Augusto da Luz Reis; Luciano Ost (VLSI-SOC, 2020)

Security Issues in the Design of Chips for IoT. - Calebe Micael de Oliveira Conceição; Ricardo Augusto da Luz Reis (WF-IoT, 2020)

On the superiority of modularity-based clustering for determining placement-relevant clusters. - Mateus Fogaça; Andrew B. Kahng; Eder Monteiro; Ricardo Reis 001; Lutong Wang; Mingyu Woo (Integr., 2020)

Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology. - Leonardo Heitich Brendler; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Augusto da Luz Reis (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Sensitivity of FinFET Adders to PVT Variations and Sleep Transistor as a Mitigation Strategy. - Gerson D. Andrade; Ricardo A. L. Reis; Eduardo A. C. da Costa; Alexandra L. Zimpeck (APCCAS, 2021)

The Impact of Precision Bitwidth on the Soft Error Reliability of the MobileNet Network. - Geancarlo Abich; Ricardo Reis 001; Luciano Ost (LASCAS, 2021)

Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit. - Leonardo Heitich Brendler; Alexandra L. Zimpeck; Fernanda Lima Kastensmidt; Cristina Meinhardt; Ricardo A. L. Reis (LASCAS, 2021)

Current Behavior on Process Variability Aware FinFET Inverter Designs. - Leonardo B. Moraes; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Reis 001 (LASCAS, 2021)

Benchmarking Open Access VLSI Partitioning Tools. - Isadora Oliveira; Marcelo Danigno; Paulo F. Butzen; Ricardo Reis 001 (LASCAS, 2021)

SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology. - Rafael N. M. Oliveira; Fábio G. R. G. da Silva; Ricardo Reis 001; Cristina Meinhardt (LATS, 2021)

Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study. - Bernardo Borges Sandoval; Leonardo Heitich Brendler; Alexandra L. Zimpeck; Fernanda Lima Kastensmidt; Ricardo Reis 001; Cristina Meinhardt (LATS, 2021)

Exploring a New Tool for Automatic Layout Synthesis for FDSOI 28 nm. - Vitor Hugo F. Maciel; Germano Girondi; Elias de Almeida Ramos; Ricardo Reis 001 (VLSI-SoC, 2021)

Evaluation of the soft error assessment consistency of a JIT-based virtual platform simulator. - Geancarlo Abich; Rafael Garibotti; Vitor V. Bandeira; Felipe da Rosa 001; Jonas Gava; Felipe T. Bortolon; Guilherme Medeiros; Fernando Moraes 001; Ricardo Reis 001; Luciano Ost (IET Comput. Digit. Tech., 2021)

Applying Lightweight Soft Error Mitigation Techniques to Embedded Mixed Precision Deep Neural Networks. - Geancarlo Abich; Jonas Gava; Rafael Garibotti; Ricardo Reis 001; Luciano Ost (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

An Extensive Soft Error Reliability Analysis of a Real Autonomous Vehicle Software Stack. - Vitor V. Bandeira; Isadora Oliveira; Felipe Rosa 001; Ricardo Reis 001; Luciano Ost (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Soft Error Assessment of CNN Inference Models Running on a RISC-V Processor. - Jonas Gava; Guilherme Dorneles; Ricardo Reis 001; Rafael Garibotti; Luciano Ost (ICECS 2022, 2022)

Research Experience as a Way to Improve Retention and Graduation Rates. - Ricardo Reis 001 (ISCAS, 2022)

Soft Error Reliability Assessment of Lightweight Cryptographic Algorithms for IoT Edge Devices. - Vinícius Da Rocha; Nicolas Moura; Jonas Gava; Vitor V. Bandeira; Luciano Ost; Ricardo Augusto da Luz Reis; Rafael Garibotti (ISCAS, 2022)

A Lifetime of Physical Design Automation and EDA Education: ISPD 2022 Lifetime Achievement Award Bio. - Ricardo Augusto da Luz Reis (ISPD, 2022)

Physical Design Optimization, From Past to Future. - Ricardo Augusto da Luz Reis (ISPD, 2022)

Impact of Thread Parallelism on the Soft Error Reliability of Convolution Neural Networks. - Geancarlo Abich; Rafael Garibotti; Jonas Gava; Ricardo Reis 001; Luciano Ost (LASCAS, 2022)

Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing. - Rafael N. M. Oliveira; Fábio G. R. G. da Silva; Ricardo Reis 001; Rafael B. Schvittz; Cristina Meinhardt (SBCCI, 2022)

Investigation of Hybrid Soft Error Mitigation Techniques for Applications running on Resource-constrained devices. - Jonas Gava; Ricardo Reis 001; Luciano Ost (VLSI-SoC, 2022)

Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology. - Fábio G. R. G. da Silva; Rafael N. M. Oliveira; Alexandra L. Zimpeck; Cristina Meinhardt; Ricardo Reis 001 (Integr., 2022)

SOFIA: An automated framework for early soft error assessment, identification, and mitigation. - Jonas Gava; Vitor V. Bandeira; Felipe Rosa 001; Rafael Garibotti; Ricardo Reis 001; Luciano Ost (J. Syst. Archit., 2022)

The Impact of Soft Errors in Memory Units of Edge Devices Executing Convolutional Neural Networks. - Geancarlo Abich; Rafael Garibotti; Ricardo Reis 001; Luciano Ost (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Tool for Automatic Radiation-Hardened SRAM Layout Generation. - Leonardo Heitich Brendler; Hervé Lapuyade; Yann Deval; Ricardo Reis 001; François Rivet (ICECS, 2023)

Impact on Radiation Robustness of Gate Mapping in FinFET Circuits under Work-function Fluctuation. - Bernardo Borges Sandoval; Leonardo Heitich Brendler; Fernanda Lima Kastensmidt; Ricardo Reis 001; Alexandra L. Zimpeck; Rafael B. Schvittz; Cristina Meinhardt (ISCAS, 2023)

Power, Performance and Reliability Evaluation of Multi-thread Machine Learning Inference Models Executing in Multicore Edge Devices. - Geancarlo Abich; Anderson Ignacio da Silva; José Eduardo Thums; Rafael da Silva; Altamiro Amadeu Susin; Ricardo Reis 001; Luciano Ost (ISVLSI, 2023)

A MCU-robust Interleaved Data/Detection SRAM for Space Environments. - Leonardo Heitich Brendler; Hervé Lapuyade; Yann Deval; Ricardo Reis 001; François Rivet (ISVLSI, 2023)

Using Lyapunov Exponents and Entropy to Estimate Sensitivity to Process Variability. - Elias de Almeida Ramos; Ricardo Reis 001 (ISVLSI, 2023)

LEX - A Cell Switching Arcs Extractor: A Simple SPICE-Input Interface for Electrical Characterization. - Rodrigo N. Wuerdig; Vitor Hugo F. Maciel; Ricardo Reis 001; Sergio Bampi (ISVLSI, 2023)

Using Lyapunov Exponents to Estimate Sensitivity to Process Variability. - Elias de Almeida Ramos; Ricardo Reis 001 (LASCAS, 2023)

Power and Performance Costs of Radiation-Hardened ML Inference Models Running on Edge Devices. - Geancarlo Abich; Anderson Ignacio da Silva; Jonas Gava; Altamiro Amadeu Susin; Ricardo Augusto da Luz Reis; Luciano Ost (SBCCI, 2023)

An Energy-Efficient Interpolation Unit Targeting VVC Encoders with Approximate Adder. - Rafael da Silva; Mateus Grellert; Ricardo Reis 001 (SBCCI, 2023)

DeBaTE-FI: A Debugger-Based Fault Injector Infrastructure for IoT Soft Error Reliability Assessment. - Alex Hanneman; Jonas Gava; Vitor V. Bandeira; Rafael Garibotti; Ricardo Reis 001; Luciano Ost (WF-IoT, 2023)

A Proof-of-Concept of a Multiple-Cell Upsets Detection Method for SRAMs in Space Applications. - Leonardo Heitich Brendler; Hervé Lapuyade; Yann Deval; Frédéric Darracq; Frédéric Fauquet; Ricardo Reis 001; François Rivet (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Soft Error Assessment of UAV Control Algorithms Running in Resource-Constrained Microprocessors. - Alex Hanneman; Jonas Gava; Paulo Vancin; Aqsa Kk Kaim-Khani; Sam Amiri; Rafael Garibotti; Fernando Moraes 001; Ney Calazans; Ricardo Reis 001; Luciano Ost (ISVLSI, 2024)

Energy-Efficient Design of Approximate VVC Interpolation Filters Units. - Rafael da Silva; Mateus Grellert; Ricardo Reis 001 (ISVLSI, 2024)

Early Soft Error Reliability Assessment of Convolutional Neural Networks Executing on Resource-constrained IoT Edge Devices. - Geancarlo Abich; Ricardo Augusto da Luz Reis; Luciano Ost (ITC, 2024)

Comparing the Effects of Process Variability in FinFETs and CNFETs. - Elias de Almeida Ramos; Ricardo Reis 001 (LASCAS, 2024)

NEATRouter: A New Method for 2D Global Routing. - Luis Enrique Murillo Vizcardo; Ricardo Reis 001 (VLSI-SoC, 2024)

A Deterministic Model for Random Telegraph Noise. - Elias Ramos; Wilian Padilha; Augusto Weber; Fredy Morales; João B. Martins; Ricardo Reis 001 (LASCAS, 2025)

A New Metric for Estimating the Effects of Process Variability and Applications in Radiation-Tolerant Digital Circuits. - Elias Ramos; Augusto Weber; Wilian Padilha; João B. Martins; Ricardo Reis 001 (NewCAS, 2025)

Cross-Layer Approximate Design of Low-Power Fractional Motion Estimation Accelerators for VVC. - Rafael da Silva; Pedro T. L. Pereira; Mateus Grellert; Ricardo Augusto da Luz Reis (IEEE Trans. Very Large Scale Integr. Syst., 2025)