SenToy: a tangible interface to control the emotions of a synthetic character. - Ana Paiva 001; Ricardo Chaves; Moisés Piedade; Adrian Bullock; Gerd Andersson; Kristina Höök (AAMAS, 2003)

FantasyA and SenToy. - Kristina Höök; Adrian Bullock; Ana Paiva 001; Marco Vala; Ricardo Chaves; Rui Prada (CHI Extended Abstracts, 2003)

RDSP: A RISC DSP based on Residue Number System. - Ricardo Chaves; Leonel Sousa (DSD, 2003)

Towards tangibility in gameplay: building a tangible affective interface for a computer game. - Ana Paiva 001; Rui Prada; Ricardo Chaves; Marco Vala; Adrian Bullock; Gerd Andersson; Kristina Höök (ICMI, 2003)

Demo: playingfFantasyA with senToy. - Ana Paiva 001; Rui Prada; Ricardo Chaves; Marco Vala; Adrian Bullock; Gerd Andersson; Kristina Höök (ICMI, 2003)

SenToy: an affective sympathetic interface. - Ana Paiva 001; Marco Costa 002; Ricardo Chaves; Moisés Piedade; Dário Mourão; Daniel Sobral; Kristina Höök; Gerd Andersson; Adrian Bullock (Int. J. Hum. Comput. Stud., 2003)

{2n+1, sn+k, sn-1}: A New RNS Moduli Set Extension. - Ricardo Chaves; Leonel Sousa (DSD, 2004)

A universal architecture for designing efficient modulo 2n+1 multipliers. - Leonel Sousa; Ricardo Chaves (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Corrections to "A Universal Architecture for Designing Efficient Modulo 2n+1 Multipliers". - Leonel Sousa; Ricardo Chaves (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Improving SHA-2 Hardware Implementations. - Ricardo Chaves; Georgi Kuzmanov; Leonel Sousa; Stamatis Vassiliadis (CHES, 2006)

Reconfigurable memory based AES co-processor. - Ricardo Chaves; Georgi Kuzmanov; Stamatis Vassiliadis; Leonel Sousa (IPDPS, 2006)

Rescheduling for Optimized SHA-1 Calculation. - Ricardo Chaves; Georgi Kuzmanov; Leonel Sousa; Stamatis Vassiliadis (SAMOS, 2006)

Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures. - Ricardo Chaves; Leonel Sousa (IET Comput. Digit. Tech., 2007)

Merged Computation for Whirlpool Hashing. - Ricardo Chaves; Georgi Kuzmanov; Leonel Sousa; Stamatis Vassiliadis (DATE, 2008)

On-the-fly attestation of reconfigurable hardware. - Ricardo Chaves; Georgi Kuzmanov; Leonel Sousa (FPL, 2008)

Efficient FPGA elliptic curve cryptographic processor over GF(2m). - Samuel Antao; Ricardo Chaves; Leonel Sousa (FPT, 2008)

BRAM-LUT Tradeoff on a Polymorphic DES Design. - Ricardo Chaves; Blagomir Donchev; Georgi Kuzmanov; Leonel Sousa; Stamatis Vassiliadis (HiPEAC, 2008)

Vectorized AES Core for High-throughput Secure Environments. - Miquel Pericàs; Ricardo Chaves; Georgi Gaydadjiev; Stamatis Vassiliadis; Mateo Valero (VECPAR, 2008)

Cost-Efficient SHA Hardware Accelerators. - Ricardo Chaves; Georgi Kuzmanov; Leonel Sousa; Stamatis Vassiliadis (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Compact and Flexible Microcoded Elliptic Curve Processor for Reconfigurable Devices. - Samuel Antao; Ricardo Chaves; Leonel Sousa (FCCM, 2009)

Arithmetic Units for RNS Moduli {2n-3} and {2n+3} Operations. - Pedro Miguens Matutino; Ricardo Chaves; Leonel Sousa (DSD, 2010)

An improved RNS reverse converter for the {22n+1-1, 2n, 2n-1} moduli set. - Kazeem Alagbe Gbolagade; Ricardo Chaves; Leonel Sousa; Sorin Dan Cotofana (ISCAS, 2010)

An improved RNS generator 2n +/- k based on threshold logic. - Héctor Pettenghi; Ricardo Chaves; Leonel Sousa; Maria J. Avedillo (VLSI-SoC, 2010)

Binary-to-RNS Conversion Units for moduli {2^n ± 3}. - Pedro Miguens Matutino; Ricardo Chaves; Leonel Sousa (DSD, 2011)

Compact CLEFIA Implementation on FPGAS. - Paulo Proenca; Ricardo Chaves (FPL, 2011)

RNS Arithmetic Units for Modulo {2^n+-k}. - Pedro Miguens Matutino; Héctor Pettenghi; Ricardo Chaves; Leonel Sousa (DSD, 2012)

A compact and scalable RNS architecture. - Pedro Miguens Matutino; Ricardo Chaves; Leonel Sousa (ASAP, 2013)

Scalable and high throughput biosensing platform. - José M. Leitão; José A. Germano; Nuno Roma; Ricardo Chaves; Pedro Tomás (FPL, 2013)

A flexible shared library profiler for early estimation of performance gains in heterogeneous systems. - Adrian Matoga; Ricardo Chaves; Pedro Tomás; Nuno Roma (HPCS, 2013)

Transparent Application Acceleration by Intelligent Scheduling of Shared Library Calls on Heterogeneous Systems. - João Colaço; Adrian Matoga; Aleksandar Ilic; Nuno Roma; Pedro Tomás; Ricardo Chaves (PPAM (1), 2013)

HotStream: Efficient Data Streaming of Complex Patterns to Multiple Accelerating Kernels. - Sergio Paiagua; Frederico Pratas; Pedro Tomás; Nuno Roma; Ricardo Chaves (SBAC-PAD, 2013)

RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to (8n+1)-bit. - Héctor Pettenghi; Ricardo Chaves; Leonel Sousa (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Method to Design General RNS Reverse Converters for Extended Moduli Sets. - Héctor Pettenghi; Ricardo Chaves; Leonel Sousa (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

On the Design of RNS Reverse Converters for the Four-Moduli Set ${ bf {2^{ mmb n}+1, 2^{ mmb n}-1, 2^{ mmb n}, 2^{{ mmb n}+1}+1 }}$. - Leonel Sousa; Samuel Antao; Ricardo Chaves (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Accelerating differential power analysis on heterogeneous systems. - João Amaral; Francesco Regazzoni 001; Pedro Tomás; Ricardo Chaves (WESS, 2014)

Secure partial dynamic reconfiguration with unsecured external memory. - Hirak J. Kashyap; Ricardo Chaves (FPL, 2014)

Method for designing multi-channel RNS architectures to prevent power analysis SCA. - Héctor Pettenghi; Jude Angelo Ambrose; Ricardo Chaves; Leonel Sousa (ISCAS, 2014)

ROM-less RNS-to-binary converter moduli {22n - 1, 22n + 1, 2n - 3, 2n + 3}. - Pedro Miguens Matutino; Ricardo Chaves; Leonel Sousa (ISIC, 2014)

An Efficient Scalable RNS Architecture for Large Dynamic Ranges. - Pedro Miguens Matutino; Ricardo Chaves; Leonel Sousa (J. Signal Process. Syst., 2014)

Dual CLEFIA/AES Cipher Core on FPGA. - João Carlos Resende; Ricardo Chaves (ARC, 2015)

CLEFIA Implementation with Full Key Expansion. - João Carlos Bittencourt; João Carlos Resende; Wagner Luiz Alves de Oliveira; Ricardo Chaves (DSD, 2015)

Compact dual block AES core on FPGA for CCM Protocol. - João Carlos Resende; Ricardo Chaves (FPL, 2015)

Challenges in designing trustworthy cryptographic co-processors. - Ricardo Chaves; Giorgio Di Natale; Lejla Batina; Shivam Bhasin; Baris Ege; Apostolos P. Fournaris; Nele Mentens; Stjepan Picek; Francesco Regazzoni 001; Vladimir Rozic; Nicolas Sklavos 001; Bohan Yang 001 (ISCAS, 2015)

Morphable hundred-core heterogeneous architecture for energy-aware computation. - Nuno Neves 002; Henrique Mendes; Ricardo Chaves; Pedro Tomás; Nuno Roma (IET Comput. Digit. Tech., 2015)

Arithmetic-Based Binary-to-RNS Converter Modulo {2n±k} for jn-bit Dynamic Range. - Pedro Miguens Matutino; Ricardo Chaves; Leonel Sousa (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Global Identity and Reachability Framework for Interoperable P2P Communication Services. - Ibrahim Tariq Javed; Rebecca Copeland; Noël Crespi; Felix Beierle; Sebastian Göndör; Axel Küpper; Ahmed Bouabdallah; Marc Emmelmann; Andreea Ancuta Corici; Kevin Corre; Jean-Michel Crom; Frank Oberle; et al. (ICIN, 2016)

Policy-Based Management for Smart Mobility. - Teresa Vazão; João Duarte Gomes; Ricardo Chaves (Intelligent Environments (Workshops), 2016)

Storekeeper: A Security-Enhanced Cloud Storage Aggregation Service. - Sancha Pereira; André Alves; Nuno Santos 001; Ricardo Chaves (SRDS, 2016)

Low Power Montgomery Modular Multiplication on Reconfigurable Systems. - Pedro Maat C. Massolino; Lejla Batina; Ricardo Chaves; Nele Mentens (IACR Cryptol. ePrint Arch., 2016)

Method for designing two levels RNS reverse converters for large dynamic ranges. - Héctor Pettenghi; Ricardo Chaves; Roberto de Matos; Leonel Sousa (Integr., 2016)

Compact and On-the-Fly Secure Dynamic Reconfiguration for Volatile FPGAs. - Hirak J. Kashyap; Ricardo Chaves (ACM Trans. Reconfigurable Technol. Syst., 2016)

Decentralized Communications: Trustworthy interoperability in peer-to-peer networks. - Paulo Chainho; Steffen Druesedow; Ricardo Lopes Pereira; Ricardo Chaves; Nuno Santos 001; Kay Haensge; Antón Román Portabales (EuCNC, 2017)

Area-optimized montgomery multiplication on IGLOO 2 FPGAs. - Pedro Maat C. Massolino; Lejla Batina; Ricardo Chaves; Nele Mentens (FPL, 2017)

Improving FPGA based SHA-3 structures. - Magnus Sundal; Ricardo Chaves (HOST, 2017)

Efficient FPGA Implementation of the SHA-3 Hash Function. - Magnus Sundal; Ricardo Chaves (ISVLSI, 2017)

Flexible and low-cost HSM based on non-volatile FPGAs. - Diogo Parrinha; Ricardo Chaves (ReConFig, 2017)

Pipelined FPGA coprocessor for elliptic curve cryptography based on residue number system. - Pedro Miguens Matutino; Juvenal Araujo; Leonel Sousa; Ricardo Chaves (SAMOS, 2017)

Cross-domain identity and discovery framework for web calling services. - Ibrahim Tariq Javed; Rebecca Copeland; Noël Crespi; Marc Emmelmann; Andreea Ancuta Corici; Ahmed Bouabdallah; Tuo Zhang; Saad El Jaouhari; Felix Beierle; Sebastian Göndör; Axel Küpper; Kevin Corre; et al. (Ann. des Télécommunications, 2017)

SCA-Resistance for AES: How Cheap Can We Go? - Ricardo Chaves; Lukasz Chmielewski; Francesco Regazzoni 001; Lejla Batina (AFRICACRYPT, 2018)

Low-power frequency monitoring circuit for clock failure detection. - Rodrigo B. Capeleiro; José M. Leitão; Ricardo Chaves; Marcelino B. Santos (DCIS, 2018)

Applying Model Checking in the Verification of a Clock Masking Unit. - José M. Leitão; Ricardo Chaves; Marcelino B. Santos (DCIS, 2019)

TBOX-Based Mask Scrambling Against SCA. - João Carlos Resende; Ricardo J. R. Maçãs; Ricardo Chaves (FCCM, 2020)

Mask Scrambling Against SCA on Reconfigurable TBOX-Based AES. - João Carlos Resende; Ricardo J. R. Maçãs; Ricardo Chaves (FPL, 2020)

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Ricardo Chaves; Manuel Valencia-Barrero; Antonio Acosta-Jiménez; Carlos Jesús Jiménez-Fernández (ISCAS, 2020)

When Backscatter Communication Meets Vehicular Networks: Boosting Crosswalk Awareness. - Felisberto Pereira; Arnaldo S. R. Oliveira; Nuno Borges Carvalho; Hugo Sampaio; Ricardo Chaves; Ricardo Correia 003; Miguel Luís; Susana Sargento; Marina Jordão; Luís Almeida 001; Carlos R. Senna (IEEE Access, 2020)

EmuCD: An Emulator for Content Dissemination Protocols in Vehicular Networks. - Ricardo Chaves; Carlos R. Senna; Miguel Luís; Susana Sargento; André Moreira; Diogo Recharte; Ricardo Matos (Future Internet, 2020)

SmartFusion2 SoC as a security module for the IoT world. - Alexandre Rodrigues 006; João Carlos Resende; Ricardo Chaves (CF, 2022)

Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Antonio J. Acosta 001; Carlos Jesús Jiménez-Fernández; Ricardo Chaves (IEEE Access, 2022)

EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. - Fabio Pavanello; Cédric Marchand 002; Ian O'Connor; Régis Orobtchouk; Fabien Mandorlo; Xavier Letartre; Sébastien Cueff; Elena-Ioana Vatajelu; Giorgio Di Natale; Benoit Cluzel; Aurelien Coillet; Benoît Charbonnier; et al. (ETS, 2023)

Lightweight Network-Based IoT Device Authentication in Cloud Services. - Tomás Silva; João Casal; Ricardo Chaves (ICNP, 2023)

NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. - Fabio Pavanello; Cédric Marchand 002; Ian O'Connor; Régis Orobtchouk; Fabien Mandorlo; Xavier Letartre; Sébastien Cueff; Elena-Ioana Vatajelu; Giorgio Di Natale; Benoit Cluzel; Aurelien Coillet; Benoît Charbonnier; et al. (CoRR, 2023)

Content distribution in a VANET using InterPlanetary file system. - Ricardo Chaves; Carlos R. Senna; Miguel Luís; Susana Sargento; Ricardo Matos; Diogo Recharte (Wirel. Networks, 2023)

Security Layers and Related Services within the Horizon Europe NEUROPULS Project. - Fabio Pavanello; Cédric Marchand 002; Paul Jiménez; Xavier Letartre; Ricardo Chaves; Niccolò Marastoni; Alberto Lovato; Mariano Ceccato; George Papadimitriou 001; Vasileios Karakostas; Dimitris Gizopoulos; Roberta Bardini; et al. (DATE, 2024)

External Memory Protection on FPGA-Based Embedded Systems. - João Carlos Resende; Aleksandar Ilic; Ricardo Chaves (DSD, 2024)

DISCRETION: First Field Demonstration of a Quantum Enabled SDN in the Context of a Military Exercise. - Catarina Bastos; Francisco Pinto; Rodrigo Bacar; Gustavo Anjos; Margarida Almeida; Armando Nolasco Pinto; Ricardo Chaves; Tiago Dias 001; Joana Afonso; Rui Calé; Miguel Freitas; Luis Maia; et al. (ICMCIS, 2025)