Multiscale estimation of processes related to the fractional Black-Scholes equation. - Ricardo Fernández-Pascual; María Dolores Ruiz-Medina; José Miguel Angulo (Comput. Stat., 2003)

Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures. - Ricardo Fernández-Pascual; José M. García 001; Gregorio Bernabé; Manuel E. Acacio (PDP, 2005)

A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures. - Ricardo Fernández-Pascual; José M. García 001; Manuel E. Acacio; José Duato (HPCA, 2007)

An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology. - Gregorio Bernabé; Ricardo Fernández-Pascual; José M. García 001; Manuel E. Acacio; José González 002 (Parallel Comput., 2007)

A fault-tolerant directory-based cache coherence protocol for CMP architectures. - Ricardo Fernández-Pascual; José M. García 001; Manuel E. Acacio; José Duato (DSN, 2008)

Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs. - Ricardo Fernández-Pascual; José M. García 001; Manuel E. Acacio; José Duato (HiPC, 2008)

An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems. - Marco Cornero; Roberto Costa; Ricardo Fernández-Pascual; Andrea C. Ornstein; Erven Rohou (HiPEAC, 2008)

Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors. - Alberto Ros 001; Ricardo Fernández-Pascual; Manuel E. Acacio; José M. García 001 (J. Parallel Distributed Comput., 2008)

Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures. - Ricardo Fernández-Pascual; José M. García 001; Manuel E. Acacio; José Duato (IEEE Trans. Parallel Distributed Syst., 2008)

EMC2: Extending Magny-Cours coherence for large-scale servers. - Alberto Ros 001; Blas Cuesta; Ricardo Fernández-Pascual; María Engracia Gómez; Manuel E. Acacio; Antonio Robles; José M. García 001; José Duato (HiPC, 2010)

Analyzing Cache Coherence Protocols for Server Consolidation. - Antonio García-Guirado; Ricardo Fernández-Pascual; José M. García 001 (SBAC-PAD, 2010)

Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level. - Ricardo Fernández-Pascual; José M. García 001; Manuel E. Acacio; José Duato (IEEE Trans. Parallel Distributed Syst., 2010)

Energy-Efficient Cache Coherence Protocols in Chip-Multiprocessors for Server Consolidation. - Antonio García-Guirado; Ricardo Fernández-Pascual; Alberto Ros 001; José M. García 001 (ICPP, 2011)

An Experience of Early Initiation to Parallelism in the Computing Engineering Degree at the University of Murcia, Spain. - Manuel E. Acacio; Javier Cuenca 001; Lorenzo Fernández Maimó; Ricardo Fernández-Pascual; Joaquín Cervera; Domingo Giménez; M. Carmen Garrido; Juan A. Sánchez-Laguna; José Guillén; Juan Alejandro Palomino Benito; María-Eugenia Requena (IPDPS Workshops, 2012)

The Spanish Parallel Programming Contests and its Use as an Educational Resource. - Francisco Almeida; Javier Cuenca 001; Ricardo Fernández-Pascual; Domingo Giménez; Juan Alejandro Palomino Benito (IPDPS Workshops, 2012)

Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs. - Alberto Ros 001; Ricardo Fernández-Pascual; Manuel E. Acacio (SBAC-PAD, 2012)

DAPSCO: Distance-aware partially shared cache organization. - Antonio García-Guirado; Ricardo Fernández-Pascual; Alberto Ros 001; José M. García 001 (ACM Trans. Archit. Code Optim., 2012)

Extending Magny-Cours Cache Coherence. - Alberto Ros 001; Blas Cuesta Saez; Ricardo Fernández-Pascual; María Engracia Gómez; Manuel E. Acacio; Antonio Robles; José M. García 001; José Duato (IEEE Trans. Computers, 2012)

Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs. - Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (Euro-Par Workshops (2), 2014)

Managing resources dynamically in hybrid photonic-electronic networks-on-chip. - Antonio García-Guirado; Ricardo Fernández-Pascual; José M. García 001; Sandro Bartolini (Concurr. Comput. Pract. Exp., 2014)

Early Experiences with Separate Caches for Private and Shared Data. - Juan M. Cebrian; Alberto Ros 001; Ricardo Fernández-Pascual; Manuel E. Acacio (e-Science, 2015)

ICCI: In-Cache Coherence Information. - Antonio García-Guirado; Ricardo Fernández-Pascual; José M. García 001 (IEEE Trans. Computers, 2015)

Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence. - Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (ARCS, 2016)

Plug-in prediction intervals for a special class of standard ARH(1) processes. - María Dolores Ruiz-Medina; Elvira Romano; Ricardo Fernández-Pascual (J. Multivar. Anal., 2016)

New compactly supported spatiotemporal covariance functions from SPDEs. - María Dolores Ruiz-Medina; José Miguel Angulo; George Christakos; Ricardo Fernández-Pascual (Stat. Methods Appl., 2016)

Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study. - Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (J. Supercomput., 2016)

Way-combining directory: an adaptive and scalable low-cost coherence directory. - J. Rubén Titos Gil; Antonio Flores; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (ICS, 2017)

A dedicated private-shared cache design for scalable multiprocessors. - Juan M. Cebrian; Ricardo Fernández-Pascual; Alexandra Jimborean; Manuel E. Acacio; Alberto Ros 001 (Concurr. Comput. Pract. Exp., 2017)

To be silent or not: on the impact of evictions of clean data in cache-coherent multicores. - Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (J. Supercomput., 2017)

Way Combination for an Adaptive and Scalable Coherence Directory. - J. Rubén Titos Gil; Antonio Flores; Ricardo Fernández-Pascual; Alberto Ros 001; Salvador Petit; Julio Sahuquillo; Manuel E. Acacio (IEEE Trans. Parallel Distributed Syst., 2019)

PfTouch: Concurrent page-fault handling for Intel restricted transactional memory. - J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (J. Parallel Distributed Comput., 2020)

Concurrent Irrevocability in Best-Effort Hardware Transactional Memory. - J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (IEEE Trans. Parallel Distributed Syst., 2020)

Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory. - Víctor Nicolás-Conesa; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (PDP, 2022)

Analysing software prefetching opportunities in hardware transactional memory. - Marina Shimchenko; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Manuel E. Acacio; Stefanos Kaxiras; Alberto Ros 001; Alexandra Jimborean (J. Supercomput., 2022)

DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory. - J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (IEEE Trans. Parallel Distributed Syst., 2022)

Enhanced System-Level Coherence for Heterogeneous Unified Memory Architectures. - Anoop Mysore Nataraja; Ricardo Fernández-Pascual; Alberto Ros 001 (IISWC, 2024)

Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory. - Víctor Nicolás-Conesa; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Manuel E. Acacio; Alberto Ros 001 (MICRO, 2024)

On the interactions between ILP and TLP with hardware transactional memory. - Víctor Nicolás-Conesa; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (Microprocess. Microsystems, 2024)

WoperTM: Got Nacks? Use Them! - Víctor Nicolás-Conesa; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Manuel E. Acacio; Alberto Ros 001 (IEEE Comput. Archit. Lett., 2025)

Precise characterization of coherence activity in multicores using gem5. - Joaquín Ferrer; Juan M. Cebrian; Ricardo Fernández-Pascual; Manuel E. Acacio (J. Supercomput., 2025)