FPGA Implementation of Adaptive Non-linear Predictors for Video Compression. - Rafael Gadea Gironés; Agustín Ramírez-Agundis; Joaquín Cerdá-Boluda; Ricardo José Colom-Palero (FPL, 2003)

FPGA Custom DSP for ECG Signal Analysis and Compression. - Marcos Martínez Peiró; Francisco José Ballester-Merelo; Guillermo Payá Vayá; Ricardo José Colom-Palero; Rafael Gadea Gironés; J. Belenguer (FPL, 2004)

Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices. - Ricardo José Colom-Palero; Rafael Gadea Gironés; Francisco José Ballester-Merelo; Marcos Martínez Peiró (Microprocess. Microsystems, 2004)

FPGA Implementation of a Pipelined On-Line Backpropagation. - Rafael Gadea Gironés; Ricardo José Colom-Palero; Joaquín Cerdá-Boluda; Angel Sebastià-Cortés (J. VLSI Signal Process., 2005)

An active methodology for teaching electronic systems design. - Joaquín Cerdá-Boluda; Marcos Martínez Peiró; Miguel A. Larrea Torres; Rafael Gadea Gironés; Ricardo José Colom-Palero (IEEE Trans. Educ., 2006)

A Novel FPGA Architecture of a 2-D Wavelet Transform. - Ricardo José Colom-Palero; Rafael Gadea Gironés; Angel Sebastià-Cortés (J. VLSI Signal Process., 2006)

A wavelet-VQ system for real-time video compression. - Agustín Ramírez-Agundis; Rafael Gadea Gironés; Ricardo José Colom-Palero; Javier Díaz-Carmona (J. Real Time Image Process., 2007)

SoC-Based Implementation of the Backpropagation Algorithm for MLP. - Ramón José Aliaga; Rafael Gadea Gironés; Ricardo José Colom-Palero; José María Monzó; Christoph W. Lerche; Jorge Daniel Martínez; Angel Sebastiá; Fernando Mateo (HIS, 2008)

A Mixed Hardware/Software SOFM Training System. - Agustín Ramírez-Agundis; Rafael Gadea Gironés; Ricardo José Colom-Palero; Javier Díaz-Carmona (Computación y Sistemas, 2008)

A hardware design of a massive-parallel, modular NN-based vector quantizer for real-time video coding. - Agustín Ramírez-Agundis; Rafael Gadea Gironés; Ricardo José Colom-Palero (Microprocess. Microsystems, 2008)

A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA. - Ramón José Aliaga; Rafael Gadea Gironés; Ricardo José Colom-Palero; Joaquín Cerdá; Néstor Ferrando; Vicente Herrero-Bosch (ICSAMOS, 2009)

Optimization of Deep Neural Networks Using SoCs with OpenCL. - Rafael Gadea Gironés; Ricardo José Colom-Palero; Vicente Herrero-Bosch (Sensors, 2018)