An Environment for Exploring Data-Driven Architectures. - Ricardo S. Ferreira 001; João M. P. Cardoso; Horácio C. Neto (FPL, 2004)

A Java Framework to Teach Computer Architecture. - Ricardo S. Ferreira 001; Antonio Carlos Schneider Beck; Luigi Carro; Andre Toledo; Aroldo Silva (EDUTECH, 2005)

Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping. - Ricardo S. Ferreira 001; João M. P. Cardoso; Andre Toledo; Horácio C. Neto (SAMOS, 2005)

Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array Architectures. - Marcos Vinícius da Silva; Ricardo S. Ferreira 001; Alisson Garcia; João M. P. Cardoso (ReConFig, 2006)

A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures. - Ricardo S. Ferreira 001; Alisson Garcia; Tiago Teixeira; João M. P. Cardoso (ISVLSI, 2007)

Reducing interconnection cost in coarse-grained dynamic computing through multistage network. - Ricardo S. Ferreira 001; Marcone Laure; Mateus B. Rutzig; Antonio Carlos Schneider Beck; Luigi Carro (FPL, 2008)

On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks. - Ricardo S. Ferreira 001; Alex Damiany; Julio C. Goldner Vendramini; Tiago Teixeira; João M. P. Cardoso (ARC, 2009)

A low cost and adaptable routing network for reconfigurable systems. - Ricardo S. Ferreira 001; Marcone Laure; Antonio Carlos Schneider Beck; Thiago Lo; Mateus B. Rutzig; Luigi Carro (IPDPS, 2009)

An implementation of the multi-geo routing protocol for wireless sensor networks using quadtrees. - Vitor Barbosa C. Souza; Mauro Nacif Rocha; Ricardo Santos Ferreira 001; Carlos de Castro Goulart (PE-WASUN, 2009)

FPGA-accelerated Attractor Computation of Scale Free Gene Regulatory Networks. - Ricardo S. Ferreira 001; Julio C. Goldner Vendramini (FPL, 2010)

An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture. - Ricardo S. Ferreira 001; Julio C. Goldner Vendramini; Lucas Mucida; Monica Magalhães Pereira; Luigi Carro (CASES, 2011)

Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks. - Ricardo S. Ferreira 001; João M. P. Cardoso; Alex Damiany; Julio C. Goldner Vendramini; Tiago Teixeira (J. Syst. Archit., 2011)

Theoretical Basis of a New Method for DNA Fragment Assembly in k-mer Graphs. - Adriano Donato Couto; Fabio Ribeiro Cerqueira; Rafael Luciano Guerra; Luciana Brugiolo Gonçalves; Carlos de Castro Goulart; Rodrigo Siqueira-Batista; Ricardo dos Santos Ferreira 001; Alcione de Paiva Oliveira (SCCC, 2012)

Problem Oriented Approach to Hardware-Assisted Algorithm Design in C: A Case Study for Scheduling, Placement and Routing. - Lucas Mucida; Vincius Lopes; Waldir Meireles; Ricardo S. Ferreira 001 (WSCAD-SSC, 2012)

Multiagent Systems Modeling Using GPUs - A Case Study of the Human Immune System. - Oberlan Christo Romão; Luís Eduardo de Souza Amorim; Ricardo dos Santos Ferreira 001; Maurilio De Araujo Possi; Alcione de Paiva Oliveira (WSCAD-SSC, 2012)

A run-time graph-based Polynomial Placement and routing algorithm for virtual FPGAS. - Ricardo S. Ferreira 001; Luciana Rocha; André G. Santos; José Augusto Miranda Nacif; Stephan Wong; Luigi Carro (FPL, 2013)

A just-in-time modulo scheduling for virtual coarse-grained reconfigurable architectures. - Ricardo S. Ferreira 001; Vinicius Duarte; Waldir Meireles; Monica Magalhães Pereira; Luigi Carro; Stephan Wong (ICSAMOS, 2013)

A run-time modulo scheduling by using a binary translation mechanism. - Ricardo S. Ferreira 001; Waldir Denver; Monica Magalhães Pereira; Jorge Quadros; Luigi Carro; Stephan Wong (ICSAMOS, 2014)

Hardware Architecture Benchmarking for Simulation of Human Immune System by Multi-agent Systems. - Fábio Rodrigues Martins; Alcione de Paiva Oliveira; Ricardo dos Santos Ferreira 001; Fabio Ribeiro Cerqueira (EUMAS/AT, 2015)

Be a simulator developer and go beyond in computing engineering. - Ricardo S. Ferreira 001; José Augusto Miranda Nacif; Salles V. G. Magalhães; Thales T. de Almeida; Racyus D. G. Pacífico (FIE, 2015)

Proposal of a New Method for de Novo DNA Sequence Assembly Using de Bruijn Graphs. - Adriano Donato Couto; Fabio Ribeiro Cerqueira; Ricardo dos Santos Ferreira 001; Alcione de Paiva Oliveira (ISCIS, 2015)

Vericonn: a tool to generate efficient interconnection networks for post-silicon debug. - André B. M. Gomes; Fredy A. M. Alves; Ricardo S. Ferreira 001; José Augusto Miranda Nacif (LATS, 2015)

Increasing Observability in Post-Silicon Debug Using Asymmetric Omega Networks. - André B. M. Gomes; Fredy A. M. Alves; Ricardo S. Ferreira 001; José Augusto Miranda Nacif (SBCCI, 2015)

SBESC 2013 guest editor's introduction. - Lisane B. de Brisolara; Ricardo Santos Ferreira 001 (Des. Autom. Embed. Syst., 2015)

A Runtime FPGA Placement and Routing Using Low-Complexity Graph Traversal. - Ricardo S. Ferreira 001; Luciana Rocha; André G. Santos; José Augusto Miranda Nacif; Stephan Wong; Luigi Carro (ACM Trans. Reconfigurable Technol. Syst., 2015)

A Placement and routing algorithm for Quantum-dot Cellular Automata. - Alyson Trindade; Ricardo S. Ferreira 001; José Augusto Miranda Nacif; Douglas Sales; Omar P. Vilela Neto (SBCCI, 2016)

SBESC 2014 guest editors' introduction. - Marco Aurélio Wehrmeister; Ricardo Santos Ferreira 001 (Des. Autom. Embed. Syst., 2016)

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility. - Ricardo S. Ferreira 001; Waldir Denver; Monica Magalhães Pereira; Stephan Wong; Carlos Arthur Lang Lisbôa; Luigi Carro (J. Signal Process. Syst., 2016)

Designing a collision detection accelerator on a heterogeneous CPU-FPGA platform. - Fredy Augusto M. Alves; Peter Jamieson; Lucas B. da Silva; Ricardo S. Ferreira 001; José Augusto Miranda Nacif (ReConFig, 2017)

Exploring the dynamics of large-scale gene regulatory networks using hardware acceleration on a heterogeneous CPU-FPGA platform. - Lucas B. da Silva; Danilo Damião Almeida; José Augusto Miranda Nacif; Ismael Sanchez-Osorio; Carlos A. Hernandez-Martinez; Ricardo Ferreira 001 (ReConFig, 2017)

Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata. - Frank Sill Torres; Pedro Arthur Silva; Geraldo Fontes; José Augusto Miranda Nacif; Ricardo Santos Ferreira 001; Omar Paranaiba Vilela Neto; Jeferson F. Chaves; Rolf Drechsler (DSD, 2018)

Fast analysis of upstream features on spatial networks (GIS cup). - Salles Viana Gomes Magalhães; W. Randolph Franklin; Ricardo dos Santos Ferreira 001 (SIGSPATIAL/GIS, 2018)

Placement and Routing by Overlapping and Merging QCA Gates. - Geraldo Fontes; Pedro Arthur R. L. Silva; José Augusto Miranda Nacif; Omar P. Vilela Neto; Ricardo Ferreira 001 (ISCAS, 2018)

A Novel Five-input Multiple-function QCA Threshold Gate. - Pedro Arthur R. L. Silva; Juliana Rezende S. B. Alves; Ricardo S. Ferreira 001; Omar P. Vilela Neto; José Augusto Miranda Nacif (ISCAS, 2018)

Lessons learned on which applications benefit when implemented on CPU-FPGA heterogeneous system. - Fredy A. M. Alves; Peter Jamieson; Lucas Bragança; Ricardo Ferreira 001; José Augusto Miranda Nacif (SAMOS, 2018)

Simplifying HW/SW integration to deploy multiple accelerators for CPU-FPGA heterogeneous platforms. - Lucas Bragança; Fredy A. M. Alves; Jeronimo Costa Penha; Gabriel T. P. Coimbra; Ricardo Ferreira 001; José Augusto Miranda Nacif (SAMOS, 2018)

From Java to FPGA: An Experience with the Intel HARP System. - Pedro Caldeira; Jeronimo Costa Penha; Lucas Bragança; Ricardo Ferreira 001; José Augusto Miranda Nacif; Renato Ferreira 001; Fernando Magno Quintão Pereira (SBAC-PAD, 2018)

Minimum Switching Networks. - Ricardo Ferreira 001; Michael Canesche; Kristtopher Coelho; José Augusto Miranda Nacif (SBESC, 2018)

A GPU/FPGA-Based K-Means Clustering Using a Parameterized Code Generator. - Jeronimo Costa Penha; Lucas Bragança; Kristtopher Coelho; Michael Canesche; Jansen Silva; Giovanni Comarela; José Augusto Miranda Nacif; Ricardo Ferreira 001 (WSCAD, 2018)

Ropper: a placement and routing framework for field-coupled nanotechnologies. - Ruan Evangelista Formigoni; Ricardo S. Ferreira 001; José Augusto Miranda Nacif (SBCCI, 2019)

Bezalel - Towards low-cost pin-based shape displays. - Pedro de Almeida Sacramento; Ricardo dos Santos Ferreira 001; Marcus Vinícius Alvim Andrade (SIGGRAPH Asia Technical Briefs, 2019)

ADD: Accelerator Design and Deploy - A tool for FPGA high-performance dataflow computing. - Jeronimo Costa Penha; Lucas B. da Silva; Jansen Silva; Kristtopher Coelho; Hector P. Baranda; José Augusto Miranda Nacif; Ricardo Ferreira 001 (Concurr. Comput. Pract. Exp., 2019)

READY: A Fine-Grained Multithreading Overlay Framework for Modern CPU-FPGA Dataflow Applications. - Lucas Bragança da Silva; Ricardo S. Ferreira 001; Michael Canesche; Marcelo M. Menezes; Maria D. Vieira; Jeronimo Costa Penha; Peter Jamieson; José Augusto Miranda Nacif (ACM Trans. Embed. Comput. Syst., 2019)

A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design. - Ricardo S. Ferreira 001; Cristoferson Bueno; Marcone Laure; Monica Magalhães Pereira; Luigi Carro (Trans. High Perform. Embed. Archit. Compil., 2019)

GA-lapagos, an open-source c framework including a python-based system for data analysis. - Peter Jamieson; Ricardo S. Ferreira 001; José Augusto Miranda Nacif (GECCO Companion, 2020)

A Design Exploration of Scalable Mesh-based Fully Pipelined Accelerators. - Westerley Carvalho; Michael Canesche; Lucas Reis; Frank Sill Torres; Lucas B. da Silva; Peter Jamieson; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (FPT, 2020)

Mind the Gap: Bridging Verilog and Computer Architecture. - Fernando Passe; Michael Canesche; Omar Paranaiba Vilela Neto; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (ISCAS, 2020)

On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata. - Frank Sill Torres; Pedro Arthur Silva; Geraldo Fontes; Marcel Walter; José Augusto Miranda Nacif; Ricardo Santos Ferreira 001; Omar Paranaiba Vilela Neto; Jeferson F. Chaves; Robert Wille; Philipp Niemann 001; Daniel Große; Rolf Drechsler (Microprocess. Microsystems, 2020)

Analyzing a Low-bit rate Audio Codec - Codec2 - on an FPGA. - Peter Jamieson; Santhiya Sampath Kumar; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (CSCI, 2021)

Personalizing Online Computer Engineering Resources and Labs for Digital, Embedded, and Computer System Courses. - Peter Jamieson; Ricardo S. Ferreira 001; José Augusto Miranda Nacif (FIE, 2021)

Google Colab CAD4U: Hands-On Cloud Laboratories for Digital Design. - Michael Canesche; Lucas Bragança; Omar Paranaiba Vilela Neto; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (ISCAS, 2021)

NMLib: A Nanomagnetic Logic Standard Cell Library. - Laysson Oliveira Luz; José Augusto Miranda Nacif; Ricardo S. Ferreira 001; Omar P. Vilela Neto (ISCAS, 2021)

Is It Time to Include High-Level Synthesis Design in Digital System Education for Undergraduate Computer Engineers? - Isaac Nelson; Ricardo S. Ferreira 001; José Augusto Miranda Nacif; Peter Jamieson (ISCAS, 2021)

RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays. - Maria D. Vieira; Michael Canesche; Lucas Bragança; Josué Campos; Mateus Silva; Ricardo S. Ferreira 001; José Augusto Miranda Nacif (ISCAS, 2021)

An Open Source Custom K-means Generator for AWS Cloud FPGA Accelerators. - Lucas Bragança; Michael Canesche; Jeronimo Costa Penha; Westerley Carvalho; Giovanni Comarela; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (SBESC, 2021)

TRAVERSAL: A Fast and Adaptive Graph-Based Placement and Routing for CGRAs. - Michael Canesche; Marcelo M. Menezes; Westerley Carvalho; Frank Sill Torres; Peter Jamieson; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

HAMBug: A Hybrid CPU-FPGA System to Detect Race Conditions. - Danilo Damião Almeida; Lucas Bragança; Frank Sill Torres; Ricardo Ferreira 001; José Augusto Miranda Nacif (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

You Only Traverse Twice: A YOTT Placement, Routing, and Timing Approach for CGRAs. - Michael Canesche; Westerley Carvalho; Lucas Reis; Matheus Aguilar de Oliveira; Salles V. G. Magalhães; Peter Jamieson; José Augusto Miranda Nacif; Ricardo Ferreira 001 (ACM Trans. Embed. Comput. Syst., 2021)

A polynomial time exact solution to the bit-aware register binding problem. - Michael Canesche; Ricardo S. Ferreira 001; José Augusto Miranda Nacif; Fernando Magno Quintão Pereira (CC, 2022)

An NML in-plane Wire Crossing Structure. - Laysson Oliveira Luz; José Augusto Miranda Nacif; Ricardo S. Ferreira 001; Omar P. Vilela Neto (LASCAS, 2022)

Three-Input NPN Class Gate Library for Atomic Silicon Quantum Dots. - Maria D. Vieira; Samuel S. H. Ng; Marcel Walter; Robert Wille; Konrad Walus; Ricardo S. Ferreira 001; Omar P. Vilela Neto; José Augusto Miranda Nacif (IEEE Des. Test, 2022)

L-BANCS: A Multi-Phase Tile Design for Nanomagnetic Logic. - Ruan Evangelista Formigoni; Ricardo S. Ferreira 001; Omar P. Vilela Neto; José Augusto Miranda Nacif (ISVLSI, 2023)

A Non-Blocking Multistage Interconnection using Regular Clock Schemes for QCA Circuits. - Stefan T. Couperus Leal; Michael Canesche; Omar P. Vilela Neto; Ricardo S. Ferreira 001; José A. M. Nacif (SBCCI, 2023)

Exploring Nanomagnetic Logic with Bennett Clocking. - Pedro Arthur R. L. Silva; Jeferson F. Chaves; José Augusto Miranda Nacif; Ricardo S. Ferreira 001; Omar Paranaiba Vilela Neto (SBCCI, 2023)

RDSF: Everything at Same Place All at Once - A Random Decision Single Forest. - Olavo A. B. Silva; Alysson K. C. Silva; Ícaro G. S. Moreira; José A. M. Nacif; Ricardo S. Ferreira 001 (SBESC, 2023)

Fast flow cloud: A stream dataflow framework for cloud FPGA accelerator overlays at runtime. - Lucas Bragança; Michael Canesche; Jeronimo Costa Penha; Josué Campos; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (Concurr. Comput. Pract. Exp., 2023)

Heterogeneous reconfigurable architectures for machine learning dataflows. - Westerley Carvalho; Michael Canesche; Lucas Reis; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (Concurr. Comput. Pract. Exp., 2023)

High-performance graphics processing unit-based strategy for tuning a unmanned aerial vehicle controller subject to time-delay constraints. - Leonardo Fagundes-Junior; Michael Canesche; Ricardo S. Ferreira 001; Alexandre Santos Brandão (Concurr. Comput. Pract. Exp., 2023)

Gene regulatory accelerators on cloud FPGA. - Jeronimo Costa Penha; Lucas Bragança; Michael Canesche; Dener Ribeiro; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (Concurr. Comput. Pract. Exp., 2023)

Robustness Analysis of Atomic Silicon Quantum Dot Logic Gates. - Arthur M. Fortini; João Gabriel O. Bicalho; Omar P. Vilela Neto; Maria D. Vieira; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (SBCCI, 2024)

A Nanomagnetic Logic based processor. - Luís Fernando Miki; Laysson Oliveira Luz; José Augusto Miranda Nacif; Ricardo S. Ferreira 001; Omar P. Vilela Neto (SBCCI, 2024)

AIoT tool integration for enriching teaching resources and monitoring student engagement. - Ricardo S. Ferreira 001; Carlos Sabino; Michael Canesche; Omar Paranaiba Vilela Neto; José Augusto Miranda Nacif (Internet Things, 2024)

Machine Learning for Unmanned Aerial Vehicles Navigation: An Overview. - Leonardo Fagundes-Junior; Kevin Braathen de Carvalho; Ricardo S. Ferreira 001; Alexandre Santos Brandão (SN Comput. Sci., 2024)

Examples and tutorials on using Google Colab and Gradio to create online interactive student-learning modules. - Ricardo S. Ferreira 001; Michael Canesche; Peter Jamieson; Omar P. Vilela Neto; José A. M. Nacif (Comput. Appl. Eng. Educ., 2024)

SmartMap: Architecture-Agnostic CGRA Mapping Using Graph Traversal and Reinforcement Learning. - Fabio T. Ramos 001; Pedro E. F. Realino; Wagner A. Junior; Alex Borges Vieira; Ricardo S. Ferreira 001; José Augusto Miranda Nacif (DATE, 2025)

Network Collapsing Placement and Routing for Field-Coupled Nanocomputing. - Ruan Evangelista Formigoni; Ricardo S. Ferreira 001; Omar P. Vilela Neto; José Augusto Miranda Nacif (LASCAS, 2025)

Bridging the Gap: Accelerating Random Forests on FPGAs with High-Bandwidth Memory. - Ícaro G. S. Moreira; Lucas Bragança; Olavo A. B. Silva; Alysson K. C. Silva; Ricardo S. Ferreira 001; José Augusto Miranda Nacif (LASCAS, 2025)

Development of More Robust and Stable Logic Gates Using Novel Parameter Values for SiDB. - Emanuel V. C. Ruella; Ricardo S. Ferreira 001; Omar P. Vilela Neto; José Augusto Miranda Nacif (LASCAS, 2025)

Work-in-Progress: RISC-V-Dilemma-1: A Hardware Trojan Benchmark Based on Seeker's Dilemma Approach. - Peter Jamieson; Suman Bhunia; Jerry Chen; Chris Lallo; Blake Rile; Ricardo S. Ferreira 001; Guilherme A. S. Wilke; José A. M. Nacif; Ahmad Patooghy; Abdel-Hameed A. Badawy (SAT-CPS@CODASPY, 2025)

Reconfigurable Domain-Specific Architectures Based on Coarse-Grained Operators in High-Performance FPGAs. - Lucas Bragança da Silva; César Grandis; Jeronimo Penha; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (Concurr. Comput. Pract. Exp., 2025)

Unblocking Placement and Routing in Rearrangeable Multi-Stage Networks. - Caio Von Rondow Morais; Jeronimo Penha; José Augusto Miranda Nacif; Ricardo S. Ferreira 001 (Concurr. Comput. Pract. Exp., 2025)