Ricardo S. Ferreira

Orcid: 0000-0003-1802-7829

Affiliations:
  • Federal University of Viçosa, Minas Gerais, Brazil


According to our database1, Ricardo S. Ferreira authored at least 69 papers between 2004 and 2024.

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Bibliography

2024
Machine Learning for Unmanned Aerial Vehicles Navigation: An Overview.
SN Comput. Sci., 2024

2023
Gene regulatory accelerators on cloud FPGA.
Concurr. Comput. Pract. Exp., 2023

High-performance graphics processing unit-based strategy for tuning a unmanned aerial vehicle controller subject to time-delay constraints.
Concurr. Comput. Pract. Exp., 2023

Heterogeneous reconfigurable architectures for machine learning dataflows.
Concurr. Comput. Pract. Exp., 2023

Fast flow cloud: A stream dataflow framework for cloud FPGA accelerator overlays at runtime.
Concurr. Comput. Pract. Exp., 2023

RDSF: Everything at Same Place All at Once - A Random Decision Single Forest.
Proceedings of the XIII Brazilian Symposium on Computing Systems Engineering, 2023

Exploring Nanomagnetic Logic with Bennett Clocking.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

A Non-Blocking Multistage Interconnection using Regular Clock Schemes for QCA Circuits.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

L-BANCS: A Multi-Phase Tile Design for Nanomagnetic Logic.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

2022
Three-Input NPN Class Gate Library for Atomic Silicon Quantum Dots.
IEEE Des. Test, 2022

An NML in-plane Wire Crossing Structure.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

A polynomial time exact solution to the bit-aware register binding problem.
Proceedings of the CC '22: 31st ACM SIGPLAN International Conference on Compiler Construction, Seoul, South Korea, April 2, 2022

2021
You Only Traverse Twice: A YOTT Placement, Routing, and Timing Approach for CGRAs.
ACM Trans. Embed. Comput. Syst., 2021

HAMBug: A Hybrid CPU-FPGA System to Detect Race Conditions.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

TRAVERSAL: A Fast and Adaptive Graph-Based Placement and Routing for CGRAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

An Open Source Custom K-means Generator for AWS Cloud FPGA Accelerators.
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021

RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Is It Time to Include High-Level Synthesis Design in Digital System Education for Undergraduate Computer Engineers?
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

NMLib: A Nanomagnetic Logic Standard Cell Library.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Google Colab CAD4U: Hands-On Cloud Laboratories for Digital Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Personalizing Online Computer Engineering Resources and Labs for Digital, Embedded, and Computer System Courses.
Proceedings of the IEEE Frontiers in Education Conference, 2021

2020
On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata.
Microprocess. Microsystems, 2020

Mind the Gap: Bridging Verilog and Computer Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Design Exploration of Scalable Mesh-based Fully Pipelined Accelerators.
Proceedings of the International Conference on Field-Programmable Technology, 2020

GA-lapagos, an open-source c framework including a python-based system for data analysis.
Proceedings of the GECCO '20: Genetic and Evolutionary Computation Conference, 2020

2019
A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design.
Trans. High Perform. Embed. Archit. Compil., 2019

READY: A Fine-Grained Multithreading Overlay Framework for Modern CPU-FPGA Dataflow Applications.
ACM Trans. Embed. Comput. Syst., 2019

ADD: Accelerator Design and Deploy - A tool for FPGA high-performance dataflow computing.
Concurr. Comput. Pract. Exp., 2019

Bezalel - Towards low-cost pin-based shape displays.
Proceedings of the SIGGRAPH Asia 2019 Technical Briefs, 2019

Ropper: a placement and routing framework for field-coupled nanotechnologies.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

2018
A GPU/FPGA-Based K-Means Clustering Using a Parameterized Code Generator.
Proceedings of the Symposium on High Performance Computing Systems, 2018

Minimum Switching Networks.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

From Java to FPGA: An Experience with the Intel HARP System.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

Simplifying HW/SW integration to deploy multiple accelerators for CPU-FPGA heterogeneous platforms.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Lessons learned on which applications benefit when implemented on CPU-FPGA heterogeneous system.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

A Novel Five-input Multiple-function QCA Threshold Gate.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Placement and Routing by Overlapping and Merging QCA Gates.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Fast analysis of upstream features on spatial networks (GIS cup).
Proceedings of the 26th ACM SIGSPATIAL International Conference on Advances in Geographic Information Systems, 2018

Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017
Exploring the dynamics of large-scale gene regulatory networks using hardware acceleration on a heterogeneous CPU-FPGA platform.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Designing a collision detection accelerator on a heterogeneous CPU-FPGA platform.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

2016
A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility.
J. Signal Process. Syst., 2016

SBESC 2014 guest editors' introduction.
Des. Autom. Embed. Syst., 2016

A Placement and routing algorithm for Quantum-dot Cellular Automata.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

2015
A Runtime FPGA Placement and Routing Using Low-Complexity Graph Traversal.
ACM Trans. Reconfigurable Technol. Syst., 2015

SBESC 2013 guest editor's introduction.
Des. Autom. Embed. Syst., 2015

Increasing Observability in Post-Silicon Debug Using Asymmetric Omega Networks.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Vericonn: a tool to generate efficient interconnection networks for post-silicon debug.
Proceedings of the 16th Latin-American Test Symposium, 2015

Proposal of a New Method for de Novo DNA Sequence Assembly Using de Bruijn Graphs.
Proceedings of the Information Sciences and Systems 2015, 2015

Be a simulator developer and go beyond in computing engineering.
Proceedings of the 2015 IEEE Frontiers in Education Conference, 2015

Hardware Architecture Benchmarking for Simulation of Human Immune System by Multi-agent Systems.
Proceedings of the Multi-Agent Systems and Agreement Technologies, 2015

2014
A run-time modulo scheduling by using a binary translation mechanism.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

2013
A just-in-time modulo scheduling for virtual coarse-grained reconfigurable architectures.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

A run-time graph-based Polynomial Placement and routing algorithm for virtual FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Multiagent Systems Modeling Using GPUs - A Case Study of the Human Immune System.
Proceedings of the 13th Symposium on Computer Systems, 2012

Problem Oriented Approach to Hardware-Assisted Algorithm Design in C: A Case Study for Scheduling, Placement and Routing.
Proceedings of the 13th Symposium on Computer Systems, 2012

Theoretical Basis of a New Method for DNA Fragment Assembly in k-mer Graphs.
Proceedings of the 31st International Conference of the Chilean Computer Science Society, 2012

2011
Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks.
J. Syst. Archit., 2011

An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture.
Proceedings of the 14th International Conference on Compilers, 2011

2010
FPGA-accelerated Attractor Computation of Scale Free Gene Regulatory Networks.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
An implementation of the multi-geo routing protocol for wireless sensor networks using quadtrees.
Proceedings of the 6th ACM International Workshop on Performance Evaluation of Wireless Ad Hoc, 2009

A low cost and adaptable routing network for reconfigurable systems.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Reducing interconnection cost in coarse-grained dynamic computing through multistage network.
Proceedings of the FPL 2008, 2008

2007
A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006
Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array Architectures.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

2005
Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping.
Proceedings of the Embedded Computer Systems: Architectures, 2005

A Java Framework to Teach Computer Architecture.
Proceedings of the New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design, 2005

2004
An Environment for Exploring Data-Driven Architectures.
Proceedings of the Field Programmable Logic and Application, 2004


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