PLL-less clock multiplier with self-adjusting phase symmetry. - Volnei A. Pedroni; Ricardo U. Pedroni (ISCAS, 2006)

Panning sorter: A minimal-size architecture for hardware implementation of 2D Data Sorting Coprocessors. - Volnei A. Pedroni; Ricardo P. Jasinski; Ricardo U. Pedroni (APCCAS, 2010)

A very efficient single-iteration oldest-out data sorter. - Volnei A. Pedroni; Ricardo P. Jasinski; Ricardo U. Pedroni (ISCAS, 2011)