A reconfigurable unit for a clustered programmable-reconfigurable processor. - Richard B. Kujoth; Chi-Wei Wang; Derek B. Gottlieb; Jeffrey J. Cook; Nicholas P. Carter (FPGA, 2004)

Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor. - Chi-Wei Wang; Nicholas P. Carter; Richard B. Kujoth; Jeffrey J. Cook; Derek B. Gottlieb (FPL, 2005)

A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor. - Richard B. Kujoth; Chi-Wei Wang; Jeffrey J. Cook; Derek B. Gottlieb; Nicholas P. Carter (Microprocess. Microsystems, 2007)