Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process. - John Turner; Richard Cliff; W. Leong; Cameron McClintock; Ninh Ngo; Khai Nguyen; Chiakang Sung; Bonnie Wang; J. Watson (FPL, 1995)

A silicon efficient FLEX 6000 programmable logic architecture. - Chiakang Sung; Richard Cliff; Joseph Huang; Bonnie Wang; Khai Nguyen; Xtaobao Wang; Kerry Veenstra; Bruce Pedersen; John Turner (CICC, 1998)

A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract). - David Jefferson; Srinivas Reddy; Christopher Lane; Ninh Ngo; Wanli Chang 003; Manuel Mijia; Ketan Zaveri; Cameron McClintock; Richard Cliff (FPGA, 1998)

A next generation architecture optimized for high density system level integration. - Richard Cliff; Srinivas Reddy; Cameron McClintock; David Jefferslon; Christopher Lane; Ketan Zaveri; Manuel Mejia; Andy Lee; Ninh Ngo; Risa Altaf; Bruce Pedersen; Frank Heile; et al. (CICC, 1999)

The StratixTM routing and logic architecture. - David M. Lewis; Vaughn Betz; David Jefferson; Andy Lee; Christopher Lane; Paul Leventis; Sandy Marquardt; Cameron McClintock; Bruce Pedersen; Giles Powell; Srinivas Reddy; Chris Wysocki; et al. (FPGA, 2003)

The Stratix II logic and routing architecture. - David M. Lewis; Elias Ahmed; Gregg Baeckler; Vaughn Betz; Mark Bourgeault; David Cashman; David R. Galloway; Mike Hutton; Christopher Lane; Andy Lee; Paul Leventis; Sandy Marquardt; et al. (FPGA, 2005)

Receiver Offset Cancellation in 90-nm PLD Integrated SERDES. - Simar Maangat; Toan Nguyen; Wilson Wong; Sergey Y. Shumarayev; Tina Tran; Tim Hoang; Richard Cliff (CICC, 2007)