Scalability and design-space analysis of a 1T-1MTJ memory cell. - Richard Dorrance; Fengbo Ren; Yuta Toriyama; Amr Amin Hafez; Chih-Kong Ken Yang; Dejan Markovic (NANOARCH, 2011)

Analysis of STT-RAM cell design with multiple MTJs per access. - Henry Park; Richard Dorrance; Amr Amin Hafez; Fengbo Ren; Dejan Markovic; Chih-Kong Ken Yang (NANOARCH, 2011)

A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs). - Fengbo Ren; Henry Park; Richard Dorrance; Yuta Toriyama; Chih-Kong Ken Yang; Dejan Markovic (ISQED, 2012)

A single-precision compressive sensing signal reconstruction engine on FPGAs. - Fengbo Ren; Richard Dorrance; Wenyao Xu; Dejan Markovic (FPL, 2013)

A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-blas on FPGAs. - Richard Dorrance; Fengbo Ren; Dejan Markovic (FPGA, 2014)

An Energy-Efficient Sparse-BLAS Coprocessor using STT-MRAM. - Richard Dorrance (2015)

A 190GFLOPS/W DSP for energy-efficient sparse-BLAS in embedded IoT. - Richard Dorrance; Dejan Markovic (VLSI Circuits, 2016)

A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. - Tanay Karnik; Dileep Kurian; Paolo A. Aseron; Richard Dorrance; Erkan Alpman; Angela Nicoara; Roman Popov; Leonid Azarenkov; Mikhail J. Moiseev; Li Zhao 002; Santosh Ghosh; Rafael Misoczki; et al. (ISSCC, 2018)

802.11g/n Compliant Fully Integrated Wake-Up Receiver With -72-dBm Sensitivity in 14-nm FinFET CMOS. - Erkan Alpman; Ahmad Khairi; Richard Dorrance; Minyoung Park; V. Srinivasa Somayazulu; Jeffrey R. Foerster; Ashoke Ravi; Jeyanandh Paramesh; Stefano Pellerano (IEEE J. Solid State Circuits, 2018)

An Ultra-Low Power, Fully Integrated Wake-Up Receiver and Digital Baseband with All-Digital Impairment Correction and -92.4dBm Sensitivity for 802.11ba. - Richard Dorrance; Renzhi Liu; K. T. Asma Beevi; Deepak Dasalukunte; Mario A. Santana Lopez; Vinod Kristem; Shahrnaz Azizi; Brent R. Carlton (VLSI Circuits, 2019)

A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs. - Richard Dorrance; Andrey Belogolovy; Hechen Wang; Xue Zhang (FPL, 2020)

An 802.11ba-Based Wake-Up Radio Receiver With Wi-Fi Transceiver Integration. - Renzhi Liu; K. T. Asma Beevi; Richard Dorrance; Deepak Dasalukunte; Vinod Kristem; Mario A. Santana Lopez; Alexander W. Min; Shahrnaz Azizi; Minyoung Park; Brent R. Carlton (IEEE J. Solid State Circuits, 2020)

A Vector Processor for Mean Field Bayesian Channel Estimation. - Deepak Dasalukunte; Richard Dorrance; Le Liang; Lu Lu 002 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

An Analysis of Complex-Valued CNNs for RF Data-Driven Wireless Device Classification. - Jun Chen; Weng-Keen Wong; Bechir Hamdaoui; Abdurrahman Elmaghbub; Kathiravetpillai Sivanesan; Richard Dorrance; Lily L. Yang (ICC, 2022)

A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference. - Hechen Wang; Renzhi Liu; Richard Dorrance; Deepak Dasalukunte; Xiaosen Liu; Dan Lake; Brent R. Carlton; May Wu (VLSI Technology and Circuits, 2022)

Low latency communication over commercially available LTE and remote driving. - Andrey Belogolovy; Deepak Dasalukunte; Richard Dorrance; Evgeny Stupachenko; Xue Zhang (CoRR, 2022)

A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference. - Hechen Wang; Renzhi Liu; Richard Dorrance; Deepak Dasalukunte; Dan Lake; Brent R. Carlton (IEEE J. Solid State Circuits, 2023)

A 2-Gb/s UWB Transceiver for Short-Range Reconfigurable FDD Wireless Networks. - Renzhi Liu; K. T. Asma Beevi; Richard Dorrance; Timothy F. Cox; Rinkle Jain; Tolga Acikalin; Zhen Zhou; Tae-Young Yang; Johanny Escobar-Pelaez; Shuhei Yamada; Kenneth P. Foust; Brent R. Carlton (IEEE J. Solid State Circuits, 2023)

An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET. - Richard Dorrance; Deepak Dasalukunte; Hechen Wang; Renzhi Liu; Brent R. Carlton (IEEE J. Solid State Circuits, 2023)

A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications. - Hechen Wang; Renzhi Liu; Richard Dorrance; Deepak Dasalukunte; Niranjan Gowda; Brent R. Carlton (VLSI Technology and Circuits, 2024)

CAMEL: Capacitive Analog In-Memory Equalization for RF Signal Processing. - Md. Shahrul Islam; Kshama Lakshmi Ranganatha; Richard Dorrance; Siddharth Joshi (ISCAS, 2025)