GPMS, a general purpose memory management system - user's memory - that is. - I. Ganapathy; Richard F. Hobson (APL, 1976)

Computing science hardware laboratories and the LSI revolution. - Richard F. Hobson (SIGCSE/CSA, 1978)

Software sympathetic chip set design. - Richard F. Hobson (AFIPS National Computer Conference, 1981)

Structured Machine Design: An Ongoing Experiement. - Richard F. Hobson (ISCA, 1981)

High-level microprogramming with APL syntax. - Richard F. Hobson; Patrick Hannon; Jonathan Thornburg 001 (MICRO, 1981)

A Directly Executable Encoding for APL. - Richard F. Hobson (ACM Trans. Program. Lang. Syst., 1984)

Multiprocessor experiments for high-speed ray tracing. - Severin Gaudet; Richard F. Hobson; Pradeep Chilka; Thomas W. Calvert (ACM Trans. Graph., 1988)

Opportunities for System and User Features in a New APL Interpreter. - Richard F. Hobson; J. D. Hoskin; R. W. Spilsbury (APL, 1989)

Refinements to the regenerative carry scheme. - Richard F. Hobson (IEEE J. Solid State Circuits, 1989)

An efficient maximum-redundancy radix-8 SRT division and square-root method. - Richard F. Hobson; Michael W. Fraser (IEEE J. Solid State Circuits, 1995)

Power Reducing Techniques for Clocked CMOS PLAs. - Richard F. Hobson (Great Lakes Symposium on VLSI, 1998)

A Greedy Router with Technology Targetable Output. - R. Balakrishnan; Richard F. Hobson (Great Lakes Symposium on VLSI, 1999)

A Multiple-Input Single-Phase Clock Flip-Flop Family. - Richard F. Hobson; Allan R. Dyck (Great Lakes Symposium on VLSI, 1999)

User selectable feature support for an embedded processor. - Allan R. Dyck; Scott Evenson; Henry Fu; Richard F. Hobson (ISCAS (1), 1999)

A parallel embedded-processor architecture for ATM reassembly. - Richard F. Hobson; P. S. Wong (IEEE/ACM Trans. Netw., 1999)

SoC Features for a Multi-Processor WCDMA Base-station Modem. - Richard F. Hobson; Allan R. Dyck; Keith L. Cheung (IWSOC, 2004)

An Area-Efficient High-Speed AES S-Box Method. - Richard F. Hobson; Scott Wakelin (IWSOC, 2005)

Signal Processing with Teams of Embedded Workhorse Processors. - Richard F. Hobson; Allan R. Dyck; Keith L. Cheung; Bill Ressl (EURASIP J. Embed. Syst., 2006)

A New Single-Ended SRAM Cell With Write-Assist. - Richard F. Hobson (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A 5T Sram Cell with 4 Power Terminals for Read/Write/Standby Assist. - Richard F. Hobson (CDES, 2009)

A Low-Power, Pulsed Domino CMOS 64-bit Adder. - Richard F. Hobson (CDES, 2010)

Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC. - Hooman Jarollahi; Richard F. Hobson (CDES, 2010)

A framework for high-speed parallel-prefix adder performance evaluation and comparison. - Richard F. Hobson (Int. J. Circuit Theory Appl., 2015)