Microprocessor cores. - Andrew Burdass; Gary Campbell; Richard Grisenthwaite; David Gwilt; Peter Harrod; Richard York (ETW, 2000)

Plenary speaker: Low power solutions for a smarter future. - Richard Grisenthwaite (SoCC, 2012)

The Milestones That Define Arm's Past, Present, and Future. - Richard Grisenthwaite (IEEE Micro, 2021)

Armed Cats: Formal Concurrency Modelling at Arm. - Jade Alglave; Will Deacon; Richard Grisenthwaite; Antoine Hacquard; Luc Maranget (ACM Trans. Program. Lang. Syst., 2021)

Relaxed virtual memory in Armv8-A. - Ben Simner; Alasdair Armstrong; Jean Pichon-Pharabod; Christopher Pulte; Richard Grisenthwaite; Peter Sewell (ESOP, 2022)

Arm Morello Evaluation Platform -Validating CHERI-based Security in a High-performance System. - Richard Grisenthwaite (HCS, 2022)

Relaxed virtual memory in Armv8-A (extended version). - Ben Simner; Alasdair Armstrong; Jean Pichon-Pharabod; Christopher Pulte; Richard Grisenthwaite; Peter Sewell (CoRR, 2022)

FP8 Formats for Deep Learning. - Paulius Micikevicius; Dusan Stosic; Neil Burgess; Marius Cornea; Pradeep Dubey; Richard Grisenthwaite; Sangwon Ha; Alexander Heinecke; Patrick Judd; John Kamalu; Naveen Mellempudi; Stuart F. Oberman; et al. (CoRR, 2022)

The Arm Morello Evaluation Platform - Validating CHERI-Based Security in a High-Performance System. - Richard Grisenthwaite; Graeme Barnes; Robert N. M. Watson; Simon W. Moore; Peter Sewell; Jonathan Woodruff (IEEE Micro, 2023)

Puss in Boots: Formalizing Arm's Virtual Memory System Architecture. - Jade Alglave; Richard Grisenthwaite; Artem Khyzha; Luc Maranget; Nikos Nikoleris (IEEE Micro, 2024)