A Virtual Hardware Handler for RTR Systems. - Richard H. Turner; Roger F. Woods; Sakir Sezer; Jean-Paul Heron (FCCM, 1999)

An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing. - Tim Courtney; Richard H. Turner; Roger F. Woods (FCCM, 2000)

Multiplexer Based Reconfiguration for Virtex Multipliers. - Tim Courtney; Richard H. Turner; Roger F. Woods (FPL, 2000)

Implementation of fixed DSP functions using the reduced coefficient multiplier. - Richard H. Turner; Tim Courtney; Roger F. Woods (ICASSP, 2001)

Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead. - Jean-Paul Heron; Roger F. Woods; Sakir Sezer; Richard H. Turner (J. VLSI Signal Process., 2001)

Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXes. - Tim Courtney; Richard H. Turner; Roger F. Woods (FCCM, 2002)

Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs. - Richard H. Turner; Roger F. Woods; Tim Courtney (FPL, 2002)

Design Flow for Efficient FPGA Reconfiguration. - Richard H. Turner; Roger F. Woods (FPL, 2003)

Highly efficient, limited range multipliers for LUT-based FPGA architectures. - Richard H. Turner; Roger F. Woods (IEEE Trans. Very Large Scale Integr. Syst., 2004)