Architecture Validation for Processors. - Richard C. Ho; C. Han Yang; Mark Horowitz; David L. Dill (ISCA, 1995)

Validation coverage analysis for complex digital designs. - Richard C. Ho; Mark Horowitz (ICCAD, 1996)

Early formal verification of conditional coverage points to identify intrinsically hard-to-verify logic. - C. Richard Ho; Michael Theobald; Martin M. Deneroff; Ron O. Dror; Joseph Gagliardo; David E. Shaw (DAC, 2008)

Hierarchical simulation-based verification of Anton, a special-purpose parallel machine. - J. P. Grossman; John K. Salmon; C. Richard Ho; Doug Ierardi; Brian Towles; Brannon Batson; Jochen Spengler; Stanley C. Wang; Rolf Mueller; Michael Theobald; Cliff Young; Joseph Gagliardo; et al. (ICCD, 2008)

Anton, a special-purpose machine for molecular dynamics simulation. - David E. Shaw; Martin M. Deneroff; Ron O. Dror; Jeffrey Kuskin; Richard H. Larson; John K. Salmon; Cliff Young; Brannon Batson; Kevin J. Bowers; Jack C. Chao; Michael P. Eastwood; Joseph Gagliardo; et al. (Commun. ACM, 2008)

Anton 2: Raising the Bar for Performance and Programmability in a Special-Purpose Molecular Dynamics Supercomputer. - David E. Shaw; J. P. Grossman; Joseph A. Bank; Brannon Batson; J. Adam Butts; Jack C. Chao; Martin M. Deneroff; Ron O. Dror; Amos Even; Christopher H. Fenton; Anthony Forte; Joseph Gagliardo; et al. (SC, 2014)

In-Datacenter Performance Analysis of a Tensor Processing Unit. - Norman P. Jouppi; Cliff Young; Nishant Patil; David A. Patterson 001; Gaurav Agrawal; Raminder Bajwa; Sarah Bates; Suresh Bhatia; Nan Boden; Al Borchers; Rick Boyle; Pierre-luc Cantin; et al. (ISCA, 2017)

In-Datacenter Performance Analysis of a Tensor Processing Unit. - Norman P. Jouppi; Cliff Young; Nishant Patil; David A. Patterson 001; Gaurav Agrawal; Raminder Bajwa; Sarah Bates; Suresh Bhatia; Nan Boden; Al Borchers; Rick Boyle; Pierre-luc Cantin; et al. (CoRR, 2017)

Chip Placement with Deep Reinforcement Learning. - Azalia Mirhoseini; Anna Goldie; Mustafa Yazgan; Joe W. J. Jiang; Ebrahim M. Songhori; Shen Wang; Young-Joon Lee; Eric Johnson; Omkar Pathak; Sungmin Bae; Azade Nazi; Jiwoo Pak; et al. (CoRR, 2020)

Warehouse-scale video acceleration: co-design and deployment in the wild. - Parthasarathy Ranganathan; Daniel Stodolsky; Jeff Calow; Jeremy Dorfman; Marisabel Guevara; Clinton Wills Smullen IV; Aki Kuusela; Raghu Balasubramanian; Sandeep Bhatia; Prakash Chauhan; Anna Cheung; In Suk Chong; et al. (ASPLOS, 2021)

Learning Semantic Representations to Verify Hardware Designs. - Shobha Vasudevan; Wenjie Jiang 001; David Bieber; Rishabh Singh; Hamid Shojaei; Richard Ho 001; Charles Sutton (NeurIPS, 2021)

A graph placement methodology for fast chip design. - Azalia Mirhoseini; Anna Goldie; Mustafa Yazgan; Joe Wenjie Jiang; Ebrahim M. Songhori; Shen Wang; Young-Joon Lee; Eric Johnson; Omkar Pathak; Azade Nazi; Jiwoo Pak; Andy Tong; et al. (Nat., 2021)