Performance Evaluation of Multiple Register Sets. - Richard J. Eickemeyer; Janak H. Patel (ISCA, 1987)

Performance Evaluation of On-Chip Register and Cache Organizations. - Richard J. Eickemeyer; Janak H. Patel (ISCA, 1988)

Performance Evaluation of Multiple Register Set Architectures and Cache Memories - Richard J. Eickemeyer (1988)

Interlock collapsing ALU for increased instruction-level parallelism. - Nadeem Malik; Richard J. Eickemeyer; Stamatis Vassiliadis (MICRO, 1992)

Instruction-level parallelism from execution interlock collapsing. - Nadeem Malik; Richard J. Eickemeyer; Stamatis Vassiliadis (SIGARCH Comput. Archit. News, 1992)

On the attributes of the SCISM organization. - Stamatis Vassiliadis; Bart Blaner; Richard J. Eickemeyer (SIGARCH Comput. Archit. News, 1992)

A load-instruction unit for pipelined processors. - Richard J. Eickemeyer; Stamatis Vassiliadis (IBM J. Res. Dev., 1993)

SCISM: A scalable compound instruction set machine. - Stamatis Vassiliadis; Bart Blaner; Richard J. Eickemeyer (IBM J. Res. Dev., 1994)

Evaluation of Multithreaded Uniprocessors for Commercial Application Environments. - Richard J. Eickemeyer; Ross E. Johnson; Steven R. Kunkel; Mark S. Squillante; Shiafun Liu (ISCA, 1996)

Evaluation of Multithreaded Processors and Thread-Switch Policies. - Richard J. Eickemeyer; Ross E. Johnson; Steven R. Kunkel; Beng-Hong Lim; Mark S. Squillante; Ching-Farn Eric Wu (ISHPC, 1997)

A multithreaded PowerPC processor for commercial servers. - John M. Borkenhagen; Richard J. Eickemeyer; Ronald N. Kalla; Steven R. Kunkel (IBM J. Res. Dev., 2000)

A performance methodology for commercial servers. - Steven R. Kunkel; Richard J. Eickemeyer; Mikko H. Lipasti; Timothy J. Mullins; Brian O'Krafka; Harold Rosenberg; Steven P. Vanderwiel; Philip L. Vitale; Larry D. Whitley (IBM J. Res. Dev., 2000)

Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. - Hans M. Jacobson; Pradip Bose; Zhigang Hu; Alper Buyuktosunoglu; Victor V. Zyuban; Richard J. Eickemeyer; Lee Eisen; John Griswell; Doug Logan; Balaram Sinharoy; Joel M. Tendler (HPCA, 2005)

Characterization of simultaneous multithreading (SMT) efficiency in POWER5. - Harry M. Mathis; Alex E. Mericas; John D. McCalpin; Richard J. Eickemeyer; Steven R. Kunkel (IBM J. Res. Dev., 2005)

POWER5 system microarchitecture. - Balaram Sinharoy; Ronald N. Kalla; Joel M. Tendler; Richard J. Eickemeyer; Jody B. Joyner (IBM J. Res. Dev., 2005)

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches. - Leland Chang; Robert K. Montoye; Yutaka Nakamura; Kevin Batson; Richard J. Eickemeyer; Robert H. Dennard; Wilfried Haensch; Damir Jamsek (IEEE J. Solid State Circuits, 2008)

Abstraction and microarchitecture scaling in early-stage power modeling. - Hans M. Jacobson; Alper Buyuktosunoglu; Pradip Bose; Emrah Acar; Richard J. Eickemeyer (HPCA, 2011)

Disaggregated and optically interconnected memory: when will it be cost effective? - Bülent Abali; Richard J. Eickemeyer; Hubertus Franke; Chung-Sheng Li; Marc Taubenblatt (CoRR, 2015)

IBM POWER8 performance and energy modeling. - R. Raghavan; Richard J. Eickemeyer; Aaron Sawdey; John Griswell; D. Parikh; S. Ramani; D. M. Daly; N. Ni; B. Rogers; Alex E. Mericas; L. Maurice; K. Vu (IBM J. Res. Dev., 2015)

IBM POWER8 processor core microarchitecture. - Balaram Sinharoy; James Van Norstrand; Richard J. Eickemeyer; Hung Q. Le; Jens Leenstra; Dung Q. Nguyen; B. Konigsburg; K. Ward; M. D. Brown; José E. Moreira; D. Levitan; S. Tung; et al. (IBM J. Res. Dev., 2015)

Energy Efficiency Boost in the AI-Infused POWER10 Processor. - Brian W. Thompto; Dung Q. Nguyen; José E. Moreira; Ramon Bertran; Hans M. Jacobson; Richard J. Eickemeyer; Rahul M. Rao; Michael Goulet; Marcy Byers; Christopher J. Gonzalez; Karthik Swaminathan; Nagu R. Dhanwada; et al. (ISCA, 2021)