An on-chip all-digital measurement circuit to characterize phase-locked loop response in 45-nm SOI. - Dennis Michael Fischette; Richard Joseph DeSantis; John H. Lee (CICC, 2009)

A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O. - Dennis Michael Fischette; Alvin Leng Sun Loke; Michael M. Oshima; Bruce Andrew Doyle; Roland Bakalski; Richard Joseph DeSantis; Anand Thiruvengadam; Charles Lin Wang; Gerry R. Talbot; Emerson S. Fang (ISSCC, 2010)

An Embedded All-Digital Circuit to Measure PLL Response. - Dennis Michael Fischette; Alvin Leng Sun Loke; Richard Joseph DeSantis; Gerry R. Talbot (IEEE J. Solid State Circuits, 2010)