MIS: A Multiple-Level Logic Optimization System. - Robert K. Brayton; Richard L. Rudell; Alberto L. Sangiovanni-Vincentelli; Albert R. Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Multiple-Valued Minimization for PLA Optimization. - Richard L. Rudell; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Multi-level logic minimization using implicit don't cares. - Karen A. Bartlett; Robert K. Brayton; Gary D. Hachtel; Reily M. Jacoby; Christopher R. Morrison; Richard L. Rudell; Alberto L. Sangiovanni-Vincentelli; Albert R. Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Efficient Implementation of a BDD Package. - Karl S. Brace; Richard L. Rudell; Randal E. Bryant (DAC, 1990)

Efficient implementation of retiming. - Narendra V. Shenoy; Richard L. Rudell (ICCAD, 1994)

The Validity of Retiming Sequential Circuits. - Vigyan Singhal; Carl Pixley; Richard L. Rudell; Robert K. Brayton (DAC, 1995)

Tutorial: Design of a Logic Synthesis System. - Richard L. Rudell (DAC, 1996)