Voltage droop reduction using throttling controlled by timing margin feedback. - Michael S. Floyd; Alan J. Drake; Robert W. Berry; Harold Chase; Richard L. Willaman; Jarom Peña (VLSIC, 2012)

Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor. - Alan J. Drake; Michael S. Floyd; Richard L. Willaman; Derek J. Hathaway; Joshua Hernandez; Crystal Soja; Marshall D. Tiner; Gary D. Carpenter; Robert M. Senger (ISLPED, 2013)

Runtime power reduction capability of the IBM POWER7+ chip. - Michael S. Floyd; Alan J. Drake; Nicole S. Schwartz; Robert W. Berry; Charles Lefurgy; Malcolm S. Ware; Karthick Rajamani; Victor V. Zyuban; Richard L. Willaman; Ruby M. Zgabay (IBM J. Res. Dev., 2013)

Design Considerations for Reconfigurable Delay Circuit to Emulate System Critical Paths. - Xiaobin Yuan; Pawel Owczarczyk; Alan J. Drake; Marshall D. Tiner; David T. Hui; John P. Pennings; Francesco A. Campisano; Richard L. Willaman; Leana M. Cropp; Rudolph D. Dussault (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Deterministic Frequency Boost and Voltage Enhancements on the POWER10TM Processor. - Brian T. Vanderpool; Phillip J. Restle; Eric J. Fluhr; Gregory S. Still; Frank Campisano; Ian Carmichael; Eric Marz; Rahul Batra; Richard L. Willaman (ISSCC, 2022)

Deterministic Frequency and Voltage Enhancements on the POWER10 Processor. - Brian T. Vanderpool; Phillip J. Restle; Eric Fluhr; Gregory S. Still; Francesco A. Campisano; Ian Charmichael; Eric Marz; Rahul Batra; Richard L. Willaman (IEEE J. Solid State Circuits, 2023)