Power Constraint Scheduling of Tests. - Richard M. Chou; Kewal K. Saluja; Vishwani D. Agrawal (VLSI Design, 1994)

Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan. - Ning Jiang; Richard M. Chou; Kewal K. Saluja (FTCS, 1995)

Sequential Circuit Testing: From DFT to SFT. - Richard M. Chou; Kewal K. Saluja (VLSI Design, 1997)

Scheduling tests for VLSI systems under power constraints. - Richard M. Chou; Kewal K. Saluja; Vishwani D. Agrawal (IEEE Trans. Very Large Scale Integr. Syst., 1997)

Testable Sequential Circuit Design: A Partition and Resynthesis Approach. - Richard M. Chou; Kewal K. Saluja (VTS, 2001)