Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale Integration. - Richard M. Sedmak; Harris L. Liebergot (IEEE Trans. Computers, 1980)

Self-Test Chip to System Level Approaches. - Richard M. Sedmak (ITC, 1982)

Probing the State of the Art. - Richard M. Sedmak; Donald E. Thomas (IEEE Des. Test, 1984)

On the Possible Limits of External Testing. - Richard M. Sedmak (ITC, 1986)

A Hierarchical, Desgin-for-Testability (DFT) Methodology for the Rapid Prototyping of Application-Specific Signal Processors (RASSP). - Richard M. Sedmak; John Evans (ITC, 1995)

Spanning the Product Life Cycle: RASSP DFT. - Richard M. Sedmak; John S. Evans (IEEE Des. Test Comput., 1996)

Unsafe board states during PC-based boundary-scan testing. - William Eklow; Richard M. Sedmak; Dan Singletary; Toai Vo (ITC, 2001)