Formal Verification of PowerPC Arrays Using Symbolic Trajectory Evaluation. - Manish Pandey; Richard Raimi; Derek L. Beatty; Randal E. Bryant (DAC, 1996)

Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation. - Manish Pandey; Richard Raimi; Randal E. Bryant; Magdy S. Abadir (DAC, 1997)

Analyzing a PowerPCTM620 Microprocessor Silicon Failure Using Model Checking. - Richard Raimi; James Lear (ITC, 1997)

Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs. - Armin Biere; Edmund M. Clarke; Richard Raimi; Yunshan Zhu (CAV, 1999)

Detecting False Timing Paths: Experiments on PowerPC Microprocessors. - Richard Raimi; Jacob A. Abraham (DAC, 1999)

Environment modeling and language universality. - Richard Raimi; Ramin Hojati; Kedar S. Namjoshi (ACM Trans. Design Autom. Electr. Syst., 2000)

Bounded Model Checking Using Satisfiability Solving. - Edmund M. Clarke; Armin Biere; Richard Raimi; Yunshan Zhu (Formal Methods Syst. Des., 2001)

Silicon Debug of a PowerPC[tm] Microprocessor Using Model Checking. - Richard Raimi; James Lear (Formal Methods Syst. Des., 2002)