Chuanjin Richard Shi
Orcid: 0000-0002-3157-3464Affiliations:
- University of Washington, Department of Electrical Engineering, Seattle, WA, USA
- Fudan University, School of Microelectronics, China
According to our database1,
Chuanjin Richard Shi
authored at least 39 papers
between 2010 and 2023.
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Bibliography
2023
IEEE Trans. Parallel Distributed Syst., September, 2023
AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
Augmenting aspect-level sentiment classification with distance-related local context input.
J. Supercomput., July, 2023
Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models.
CoRR, 2023
A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain".
IEEE J. Solid State Circuits, 2022
A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction.
Integr., 2022
A 0.021mm<sup>2</sup> 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
Design of the Class-E Power Amplifier Considering the Temperature Effect of the Transistor On-Resistance for Sensor Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain.
IEEE J. Solid State Circuits, 2021
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS.
IEEE Trans. Biomed. Circuits Syst., 2020
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation.
IEEE J. Solid State Circuits, 2020
Integr., 2020
A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
The impact of real-time clinical alerts on the compliance of anesthesia documentation: A retrospective observational study.
Comput. Methods Programs Biomed., 2020
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Integr., 2018
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Pin-Efficient 12-Bit 8-Wire 8-Level Permutation Coding for High-Speed Parallel Wireline Tranceivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2013
Reducing the latency of Lee-O'Sullivan interpolation through modified initialization.
Proceedings of the 2013 Information Theory and Applications Workshop, 2013
2012
Proceedings of the 2012 Information Theory and Applications Workshop, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2010
Mixed-signal system-on-chip verification using a recursively-verifying-modeling (RVM) methodology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010