Improving FPGA Performance and Area Using an Adaptive Logic Module. - Michael D. Hutton; Jay Schleicher; David M. Lewis; Bruce Pedersen; Richard Yuan; Sinan Kaptanoglu; Gregg Baeckler; Boris Ratchev; Ketan Padalia; Mark Bourgeault; Andy Lee; Henry Kim; et al. (FPL, 2004)

The Stratix II logic and routing architecture. - David M. Lewis; Elias Ahmed; Gregg Baeckler; Vaughn Betz; Mark Bourgeault; David Cashman; David R. Galloway; Mike Hutton; Christopher Lane; Andy Lee; Paul Leventis; Sandy Marquardt; et al. (FPGA, 2005)

Efficient SAT-based Boolean matching for FPGA technology mapping. - Sean Safarpour; Andreas G. Veneris; Gregg Baeckler; Richard Yuan (DAC, 2006)

A methodology for FPGA to structured-ASIC synthesis and verification. - Michael D. Hutton; Richard Yuan; Jay Schleicher; Gregg Baeckler; Sammy Cheung; Kar Keng Chua; Hee Kong Phoo (DATE Designers' Forum, 2006)