Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. - Robert Bailey; A. Metayer; B. Svrcek; Nandu Tendolkar; E. Wolf; Eric Fiene; Mike Alexander; Rick Woltenberg; Rajesh Raina (ITC, 2002)

Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. - Nandu Tendolkar; Rajesh Raina; Rick Woltenberg; Xijiang Lin; Bruce Swanson; Greg Aldrich (VTS, 2002)