Custom Reconfigurable Architecture Based on Virtex 5 Lookup Tables. - Rico Backasch; Christian Hochberger (ARCS, 2013)

Runtime verification for multicore SoC with high-quality trace data. - Rico Backasch; Christian Hochberger; Alexander Weiss; Martin Leucker; Richard Lasslop (ACM Trans. Design Autom. Electr. Syst., 2013)

Parallel and Pipelined Filter Operator for Hardware-Accelerated Operator Graphs in Semantic Web Databases. - Stefan Werner 001; Dennis Heinrich; Marc Stelzner; Sven Groppe; Rico Backasch; Thilo Pionteck (CIT, 2014)

Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation. - Rico Backasch; Gerald Hempel; Stefan Werner 002; Sven Groppe; Thilo Pionteck (ReConFig, 2014)

An architectural template for composing application specific datapaths at runtime. - Rico Backasch; Gerald Hempel; Christopher Blochwitz; Stefan Werner 002; Sven Groppe; Thilo Pionteck (ReConFig, 2015)

An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases. - Christopher Blochwitz; Jan Moritz Joseph; Rico Backasch; Thilo Pionteck; Stefan Werner 002; Dennis Heinrich; Sven Groppe (ReConFig, 2015)

Automated composition and execution of hardware-accelerated operator graphs. - Stefan Werner 002; Dennis Heinrich; Jannik Piper; Sven Groppe; Rico Backasch; Christopher Blochwitz; Thilo Pionteck (ReCoSoC, 2015)