An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell. - Masaki Momodomi; Yasuo Itoh; Riichiro Shirota; Yoshihisa Iwata; Ryozo Nakayama; Ryouhei Kirisawa; Tomoharu Tanaka; Seiichi Aritome; Tetsuo Endoh; Kazunori Ohuchi; Fujjo Masuoka (IEEE J. Solid State Circuits, 1989)

A high-density NAND EEPROM with block-page programming for microcomputer applications. - Yoshihisa Iwata; Masaki Momodomi; Tomoharu Tanaka; Hideko Oodaira; Yasuo Itoh; Ryozo Nakayama; Ryouhei Kirisawa; Seiichi Aritome; Tetsuo Endoh; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1990)

A 4 Mb NAND EEPROM with tight programmed Vt distribution. - Masaki Momodomi; Tomoharu Tanaka; Yoshihisa Iwata; Yoshiyuki Tanaka; Hideko Oodaira; Yasuo Itoh; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1991)

Reliability issues of flash memory cells. - Seiichi Aritome; Riichiro Shirota; Gertjan Hemink; Tetsuo Endoh; Fujio Masuoka (Proc. IEEE, 1993)

A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory. - Tomoharu Tanaka; Yoshiyuki Tanaka; Hiroshi Nakamura; Koji Sakui; Hideko Oodaira; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka; Hisashi Hara (IEEE J. Solid State Circuits, 1994)

A compact on-chip ECC for low cost flash memories. - Toru Tanzawa; Tomoharu Tanaka; Ken Takeuchi; Riichiro Shirota; Seiichi Aritome; Hiroshi Watanabe; Gertjan Hemink; Kazuhiro Shimizu; Shinji Sato; Yuji Takeuchi; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1997)

A 130-mm/2, 256-Mbit NAND flash with shallow trench isolation technology. - Kenichi Imamiya; Yoshihisa Sugiura; Hiroshi Nakamura; Toshihiko Himeno; Ken Takeuchi; Tamio Ikehashi; Kazushige Kanda; Koji Hosono; Riichiro Shirota; Seiichi Aritome; Kazuhiro Shimizu; Kazuo Hatakeyama; et al. (IEEE J. Solid State Circuits, 1999)

Test and Repair of Non-Volatile Commodity and Embedded Memories (NAND Flash Memory). - Riichiro Shirota (ITC, 2002)

A 125-mm2 1-Gb NAND flash memory with 10-MByte/s program speed. - Kenichi Imamiya; Hiroshi Nakamura; Toshihiko Himeno; Toshio Yamamura; Tamio Ikehashi; Ken Takeuchi; Kazushige Kanda; Koji Hosono; Takuya Futatsuyama; Koichi Kawai; Riichiro Shirota; Norihisa Arai; et al. (IEEE J. Solid State Circuits, 2002)

Roadmap of the Flash Memory. - Riichiro Shirota (MTDT, 2006)

Improvement of oxide reliability in NAND flash memories using tight endurance cycling with shorter idling period. - Riichiro Shirota; Bo-Jun Yang; Yung-Yueh Chiu; Yu-Ting Wu; Pin-Yao Wang; Jung-Ho Chang; Masaru Yano; Minoru Aoki; Toshiaki Takeshita; C.-Y. Wang; Ikuo Kurachi (IRPS, 2015)