A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. - Tsugio Takahashi; Tomonori Sekiguchi; Riichiro Takemura; Seiji Narui; Hiroki Fujisawa; Shinichi Miyatake; Makoto Morino; Koji Arai; Satoru Yamada; Shoji Shukuri; Masayuki Nakamura; Yoshitaka Tadaki; et al. (IEEE J. Solid State Circuits, 2001)

Phase change RAM operated with 1.5-V CMOS as low cost embedded memory. - Kenichi Osada; Takayuki Kawahara; Riichiro Takemura; Naoki Kitai; Norikatsu Takaura; Nozomu Matsuzaki; Kenzo Kurotsuchi; Hiroshi Moriya; Masahiro Moniwa (CICC, 2005)

A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup. - Satoru Hanzawa; Takeshi Sakata; Kazuhiko Kajigaya; Riichiro Takemura; Tomonori Sekiguchi; Takayuki Kawahara (ICC, 2005)

A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router. - Satoru Hanzawa; Takeshi Sakata; Kazuhiko Kajigaya; Riichiro Takemura; Takayuki Kawahara (IEEE J. Solid State Circuits, 2005)

A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers. - Riichiro Takemura; Kiyoo Itoh 001; Tomonori Sekiguchi (ISLPED, 2006)

Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. - Satoru Akiyama; Tomonori Sekiguchi; Kazuhiko Kajigaya; Satoru Hanzawa; Riichiro Takemura; Takayuki Kawahara (IEEE J. Solid State Circuits, 2006)

Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs. - Kiyoo Itoh 001; Riichiro Takemura (ICECS, 2007)

SPRAM (SPin-transfer torque RAM) design and its impact on digital systems. - Takayuki Kawahara; Riichiro Takemura; Hiromasa Takahashi; Hideo Ohno (ICECS, 2007)

2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read. - Takayuki Kawahara; Riichiro Takemura; Katsuya Miura; Jun Hayakawa; Shoji Ikeda; Young Min Lee; Ryutaro Sasaki; Yasushi Goto; Kenchi Ito; Toshiyasu Meguro; Fumihiro Matsukura; Hiromasa Takahashi; et al. (ISSCC, 2007)

Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation. - Riichiro Takemura; Kiyoo Itoh 001; Tomonori Sekiguchi; Satoru Akiyama; Satoru Hanzawa; Kazuhiko Kajigaya; Takayuki Kawahara (IEICE Trans. Electron., 2007)

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. - Takayuki Kawahara; Riichiro Takemura; Katsuya Miura; Jun Hayakawa; Shoji Ikeda; Young Min Lee; Ryutaro Sasaki; Yasushi Goto; Kenchi Ito; Toshiyasu Meguro; Fumihiro Matsukura; Hiromasa Takahashi; et al. (IEEE J. Solid State Circuits, 2008)

Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays. - Satoru Akiyama; Tomonori Sekiguchi; Riichiro Takemura; Akira Kotabe; Kiyoo Itoh 001 (ISSCC, 2009)

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. - Riichiro Takemura; Takayuki Kawahara; Katsuya Miura; Hiroyuki Yamamoto; Jun Hayakawa; Nozomu Matsuzaki; Kazuo Ono; Michihiko Yamanouchi; Kenchi Ito; Hiromasa Takahashi; Shoji Ikeda; Haruhiro Hasegawa; et al. (IEEE J. Solid State Circuits, 2010)

Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. - Akira Kotabe; Kiyoo Itoh 001; Riichiro Takemura; Ryuta Tsuchiya; Masashi Horiguchi (CICC, 2011)

Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device. - Yoshimitsu Yanagawa; Kazuo Ono; Akira Kotabe; Riichiro Takemura; Tatsuo Nakagawa; Tomio Iwasaki; Takayuki Kawahara (ISCAS, 2012)

A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing. - Satoru Akiyama; Riichiro Takemura; Tomonori Sekiguchi; Akira Kotabe; Kiyoo Itoh 001 (IEICE Trans. Electron., 2012)

0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs. - Akira Kotabe; Kiyoo Itoh 001; Riichiro Takemura (IEICE Trans. Electron., 2012)

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays. - Akira Kotabe; Riichiro Takemura; Yoshimitsu Yanagawa; Tomonori Sekiguchi; Kiyoo Itoh 001 (IEICE Trans. Electron., 2012)

Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device. - Kazuo Ono; Yoshimitsu Yanagawa; Akira Kotabe; Riichiro Takemura; Tatsuo Nakagawa; Tomio Iwasaki; Takayuki Kawahara (IEICE Trans. Electron., 2012)

Spin-transfer torque RAM technology: Review and prospect. - Takayuki Kawahara; Kenchi Ito; Riichiro Takemura; Hideo Ohno (Microelectron. Reliab., 2012)