Design of Fault Tolerant Universal Logic in QCA. - Bibhash Sen; Rijoy Mukherjee; Rajdeep Kumar Nath; Biplab K. Sikdar (ISED, 2014)

Towards Designing Reliable Universal QCA Logic in the Presence of Cell Deposition Defect. - Bibhash Sen; Rajdeep Kumar Nath; Rijoy Mukherjee; Yashraj Sahu; Biplab K. Sikdar (VLSID, 2016)

A Processing In-Memory Realization Using QCA: Proposal and Implementation. - Pritam P. Chougule; Bibhash Sen; Rijoy Mukherjee; Vijay C. Karade; P. S. Patil; Tukaram D. Dongale; Rajanish K. Kamat (CoRR, 2016)

On the reliability of majority logic structure in quantum-dot cellular automata. - Bibhash Sen; Yashraj Sahu; Rijoy Mukherjee; Rajdeep Kumar Nath; Biplab K. Sikdar (Microelectron. J., 2016)

Design of Testable Adder in Quantum-dot Cellular Automata with Fault Secure Logic. - Mrinal Goswami; Bibhash Sen; Rijoy Mukherjee; Biplab K. Sikdar (Microelectron. J., 2017)

SoK: Physical and Logic Testing Techniques for Hardware Trojan Detection. - Sree Ranjani Rajendran; Rijoy Mukherjee; Rajat Subhra Chakraborty (ASHES@CCS, 2020)

Probabilistic Hardware Trojan Attacks on Multiple Layers of Reconfigurable Network Infrastructure. - Rijoy Mukherjee; Vidya Govindan; Sandhya Koteshwara; Amitabh Das; Keshab K. Parhi; Rajat Subhra Chakraborty (J. Hardw. Syst. Secur., 2020)

APUF-BNN: An Automated Framework for Efficient Combinational Logic Based Implementation of Arbiter PUF through Binarized Neural Network. - Pranesh Santikellur; Rijoy Mukherjee; Rajat Subhra Chakraborty (ACM Great Lakes Symposium on VLSI, 2021)

Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based DNN Accelerators. - Rijoy Mukherjee; Rajat Subhra Chakraborty (IEEE Embed. Syst. Lett., 2022)

A comprehensive survey of physical and logic testing techniques for Hardware Trojan detection and prevention. - Rijoy Mukherjee; Sree Ranjani Rajendran; Rajat Subhra Chakraborty (J. Cryptogr. Eng., 2022)

Attacks on Recent DNN IP Protection Techniques and Their Mitigation. - Rijoy Mukherjee; Rajat Subhra Chakraborty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Security Vulnerabilities in AI Hardware: Threats and Countermeasures. - Rijoy Mukherjee; Sneha Swaroopa; Rajat Subhra Chakraborty (ATS, 2024)

Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis. - Sneha Swaroopa; Rijoy Mukherjee; Anushka Debnath; Rajat Subhra Chakraborty (CoRR, 2024)

HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level Synthesis. - Rijoy Mukherjee; Archisman Ghosh; Rajat Subhra Chakraborty (ACM Trans. Design Autom. Electr. Syst., 2024)

Evaluating Large Language Models for Automatic Register Transfer Logic Generation for Combinational Circuits via High-Level Synthesis. - Sneha Swaroopa; Rijoy Mukherjee; Anushka Debnath; Rajat Subhra Chakraborty (Found. Trends Electron. Des. Autom., 2025)