A distance laboratory for computer-aided design. - Rimantas Seinauskas (MSE, 1997)

Procedures for Selection of Validation Vectors on the Algorithm Level. - Vacius Jusas; Kestutis Paulikas; Rimantas Seinauskas (LATW, 2001)

Identifying Legal and Illegal States in Synchronous Sequential Circuits Using Test Generation. - Eduardas Bareisa; Kestutis Motiejunas; Rimantas Seinauskas (Informatica, 2003)

Functional Test Generation Remote Tool. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas (DSD, 2005)

The Realization-Independent Testing Based on the Black Box Fault Models. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas (Informatica, 2005)

Transition Fault Test Reuse. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas (DSD, 2006)

Transition Faults Testing Based on Functional Delay Tests. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas (DDECS, 2007)

The Criteria of Functional Delay Test Quality Assessment. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas (DSD, 2007)

Functional Test Generation Based on Combined Random and Deterministic Search Methods. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas (Informatica, 2007)

Development of Functional Delay Tests. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas (DSD, 2008)

Test generation at the algorithm-level for gate-level fault coverage. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas (Microelectron. Reliab., 2008)

Functional delay test generation based on software prototype. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas (Microelectron. Reliab., 2009)

Functional fault models for non-scan sequential circuits. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas (Microelectron. Reliab., 2011)

Evaluation of testability enhancement using software prototype. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas (IET Comput. Digit. Tech., 2012)

Functional delay test generation approach using a software prototype of the circuit. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas (Comput. Sci. Inf. Syst., 2013)

Delay fault testing using partial multiple scan chains. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas (Microelectron. Reliab., 2013)

Path delay test generation at functional level. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas (IET Comput. Digit. Tech., 2015)

Black box delay fault models for non-scan sequential circuits. - Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Liudas Motiejunas; Rimantas Seinauskas (Comput. Sci. Inf. Syst., 2018)