A scalable switched-capacitor filter implemented in 1.25- mu m technology. - Sui-Ping Shieh; Chorng-Kuang Wang; Rinaldo Castello; Paul R. Gray (IEEE J. Solid State Circuits, 1989)

A floating CMOS bandgap voltage reference for differential applications. - Marco Ferro; Franco Salerno; Rinaldo Castello (IEEE J. Solid State Circuits, 1989)

A fully differential CMOS line driver for ISDN. - Liciano Tomasini; Alberto Gola; Rinaldo Castello (IEEE J. Solid State Circuits, 1990)

A 500-nA sixth-order bandpass SC filter. - Rinaldo Castello; Alberto G. Grassi; Stefano Donati (IEEE J. Solid State Circuits, 1990)

Analog front end of an ECBM transceiver for ISDN. - Rinaldo Castello; Luciano Tomasini; Sergio Pernici; Franco Salerno; Michelangelo Mazzucco; Marco Ferro (IEEE J. Solid State Circuits, 1990)

1.5-V high-performance SC filters in BiCMOS technology. - Rinaldo Castello; Luciano Tomasini (IEEE J. Solid State Circuits, 1991)

A high-linearity 50- Omega CMOS differential driver for ISDN applications. - Rinaldo Castello; Germano Nicollini; Pierluca Monguzzi (IEEE J. Solid State Circuits, 1991)

Zero placement technique for iir switched capacitor anti-aliasing decimators. - Andrea Baschirotto; Rinaldo Castello; Federico Montecchi (Int. J. Circuit Theory Appl., 1992)

100-V high-performance amplifiers in BCD technology for SLIC applications. - Rinaldo Castello; Ferdinando Lari; Marco Siligoni; Luciano Tomasini (IEEE J. Solid State Circuits, 1992)

Tunable BiCMOS continuous-time filter for high-frequency applications. - Roberto Alini; Andrea Baschirotto; Rinaldo Castello (IEEE J. Solid State Circuits, 1992)

High-speed BiCMOS Operational Amplifier for Switched-capacitor Circuits. - Andrea Baschirotto; Roberto Alini; Rinaldo Castello; Federico Montecchi (ISCAS, 1993)

Exact Design of High-frequency SC Circuits with Low-gain Op Amps. - Andrea Baschirotto; Rinaldo Castello; Federico Montecchi (ISCAS, 1993)

Novel Linearizaiton Circuit for BiCMOS Transconductors Used in High Frequency OTA-C Filters. - Francesco Rezzi; Valerio Pisati; Rinaldo Castello; Roberto Alini (ISCAS, 1993)

A BiCMOS speech circuit with only two external components. - Rinaldo Castello; Luciano Tomasini (IEEE J. Solid State Circuits, 1993)

A CMOS low-distortion fully differential power amplifier with double nested Miller compensation. - Sergio Pernici; Germano Nicollini; Rinaldo Castello (IEEE J. Solid State Circuits, 1993)

High Speed Monolithic Read-Out System for High Energy Physics Experiments. - Andrea Baschirotto; M. Bosetti; Rinaldo Castello; Alberto Gola; Gianluigi Ezio Pessina; Pier Giorgio Rancoita; M. Rattaggi; M. Redaelli; G. Terzi (ISCAS, 1994)

Design of High-Frequency BiCMOS Continuous-Time Filters with Low-Output Impedance Transconductor. - Andrea Baschirotto; Francesco Rezzi; Roberto Alini; Rinaldo Castello (ISCAS, 1994)

A single-chip 9-32 mb/s read/write channel for disk-drive applications. - Maurizio Zuffada; Roberto Alini; Paolo Colletti; Marco Demicheli; Marco Gregori; David Moloney; Salvatore Portaluri; Fabrizio Sacchi; Sadik O. Arf; Vincent Condito; Rinaldo Castello (IEEE J. Solid State Circuits, 1995)

A 15 MHz 20 mW BiCMOS switched-capacitor biquad operating with 150 Ms/s sampling frequency. - Andrea Baschirotto; Federico Montecchi; Rinaldo Castello (IEEE J. Solid State Circuits, 1995)

A readout channel with 1 nF fully integrated capacitor for AMS space experiment. - Andrea Baschirotto; G. Boella; Rinaldo Castello; Gianluigi Ezio Pessina; Pier Giorgio Rancoita (ICECS, 1996)

A PLL-based frequency synthesizer for 160-MHz double-sampled SC filters. - Francesco Rezzi; Federico Montecchi; Rinaldo Castello (IEEE J. Solid State Circuits, 1996)

A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo. - Roberto Alini; Giorgio Betti; Ivan Bietti; Giacomino Bollati; Francesco Brianti; Angelo Dati; Marco Demicheli; Paolo Gadducci; Stefano Marchese; Emanuele Marconetti; Valerio Pisati; Maurizio Zuffada; et al. (IEEE J. Solid State Circuits, 1997)

A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-rail output swing. - Andrea Baschirotto; Rinaldo Castello (IEEE J. Solid State Circuits, 1997)

A 100-MHz 4-mW four-quadrant BiCMOS analog multiplier. - Massimo Franciotta; G. Colli; Rinaldo Castello (IEEE J. Solid State Circuits, 1997)

A 10.7-MHz BiCMOS high-Q double-sampled SC bandpass filter. - Angelo Nagari; Andrea Baschirotto; Federico Montecchi; Rinaldo Castello (IEEE J. Solid State Circuits, 1997)

A 70-mW seventh-order filter with 7-50 MHz cutoff frequency and programmable boost and group delay equalization. - Francesco Rezzi; Ivan Bietti; Marco Cazzaniga; Rinaldo Castello (IEEE J. Solid State Circuits, 1997)

A 3-V 5.4-mW BiCMOS track & hold circuit with sampling frequency up to 150 MHz. - Luca Schillaci; Andrea Baschirotto; Rinaldo Castello (IEEE J. Solid State Circuits, 1997)

A versatile high-speed bipolar charge-sensitive preamplifier for calorimeter applications. - Andrea Baschirotto; Rinaldo Castello; Gianluigi Ezio Pessina; Pier Giorgio Rancoita; A. Seidman (IEEE J. Solid State Circuits, 1998)

Measurement and modeling of Si integrated inductors. - Paolo Arcioni; Rinaldo Castello; Giuseppe De Astis; Enrico Sacchi; Francesco Svelto (IEEE Trans. Instrum. Meas., 1998)

A 450 Mbit/s EPR4 PRML read/write channel. - Marco Demicheli; Giacomino Bollati; Paolo Gadducci; L. Affortunati; Roberto Alini; G. Betti; I. Bietti; F. Brianti; Melchiorre Bruccoleri; M. Coltella; P. Demartini; Stefano Marchese; et al. (CICC, 1999)

A 1.3 GHz CMOS VCO with 28% frequency tuning. - Francesco Svelto; Stefano Deantoni; Rinaldo Castello (CICC, 1999)

A low-voltage topology for CMOS RF mixers. - Francesco Svelto; Matteo Conta; Valentina Della Torre; Rinaldo Castello (IEEE Trans. Consumer Electron., 1999)

A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi. - Giacomino Bollati; Angelo Dati; Giorgio Betti; Ivan Bietti; Francesco Brianti; Melchiorre Bruccoleri; M. Coltella; P. Demartini; Marco Demicheli; Paolo Gadducci; Stefano Marchese; Daniele Ottini; et al. (CICC, 2000)

A 1 mA, -120.5 dbc/Hz at 600 kHz from 1.9 GHz fully tuneable LC CMOS VCO. - Francesco Svelto; Stefano Deantoni; Rinaldo Castello (CICC, 2000)

High-frequency CMOS low-power single-branch continuous-time filters. - Andrea Baschirotto; Ugo Baschirotto; Rinaldo Castello (ISCAS, 2000)

A 1 V 1.2 μW 4th order bandpass switched-opamp SC filter for a cardiac pacer sensing stage. - Andrea Baschirotto; Domenico Bijno; Rinaldo Castello; Federico Montecchi (ISCAS, 2000)

Solutions for image rejection CMOS LNA. - Francesco Svelto; Giampiero Montagna; Stefano Deantoni; Giulio Braschi; Rinaldo Castello (ISCAS, 2000)

An 8mA, 3.8dB NF, 40dB gain CMOS front-end for GPS applications. - Francesco Svelto; Stefano Deantoni; Giampiero Montagna; Rinaldo Castello (ISLPED, 2000)

A 200-Ms/s 10-mW switched-capacitor filter in 0.5-μm CMOS technology. - Andrea Baschirotto; F. Severi; Rinaldo Castello (IEEE J. Solid State Circuits, 2000)

A 1.3 GHz low-phase noise fully tunable CMOS LC VCO. - Francesco Svelto; Stefano Deantoni; Rinaldo Castello (IEEE J. Solid State Circuits, 2000)

An eighth-order CMOS low-pass filter with 30-120 MHz tuning range and programmable boost. - Giacomino Bollati; Stefano Marchese; Marco Demicheli; Rinaldo Castello (IEEE J. Solid State Circuits, 2001)

A 2-dB noise figure 900-MHz differential CMOS LNA. - Francesco Gatta; Enrico Sacchi; Francesco Svelto; Paolo Vilmercati; Rinaldo Castello (IEEE J. Solid State Circuits, 2001)

Implementation of a CMOS LNA plus mixer for GPS applications with no external components. - Francesco Svelto; Stefano Deantoni; Giampiero Montagna; Rinaldo Castello (IEEE Trans. Very Large Scale Integr. Syst., 2001)

An UMTS ΣΔ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques. - Ivan Bietti; Enrico Temporiti; Guido Albasini; Rinaldo Castello (CICC, 2003)

A 15 mW, 70 kHz 1/f corner direct conversion CMOS receiver. - Enrico Sacchi; Ivan Bietti; Simone Erbat; Luns Tee; Paolo Vilmercati; Rinaldo Castello (CICC, 2003)

A 35-mW 3.6-mm2 fully integrated 0.18-μm CMOS GPS radio. - Giampiero Montagna; Giuseppe Gramegna; Ivan Bietti; Massimo Franciotta; Andrea Baschirotto; Placido De Vita; Roberto Pelleriti; Mario Paparo; Rinaldo Castello (IEEE J. Solid State Circuits, 2003)

A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications. - Enrico Temporiti; Guido Albasini; Ivan Bietti; Rinaldo Castello; Matteo Colombo (IEEE J. Solid State Circuits, 2004)

A 72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner. - Mario Valla; Giampiero Montagna; Rinaldo Castello; Riccardo Tonietto; Ivan Bietti (IEEE J. Solid State Circuits, 2005)

Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End. - Antonio Liscidini; Cesare Ghezzi; Emanuele Depaoli; Guido Albasini; Ivan Bietti; Rinaldo Castello (CICC, 2006)

A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO. - Antonio Liscidini; Andrea Mazzanti; Riccardo Tonietto; Luca Vandi; Pietro Andreani; Rinaldo Castello (ISSCC, 2006)

A 0.13 μm CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier. - Antonio Liscidini; Massimo Brandolini; Davide Sanzogni; Rinaldo Castello (IEEE J. Solid State Circuits, 2006)

Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell. - Antonio Liscidini; Andrea Mazzanti; Riccardo Tonietto; Luca Vandi; Pietro Andreani; Rinaldo Castello (IEEE J. Solid State Circuits, 2006)

A fully digital fast convergence algorithm for nonlinearity correction in multistage ADC. - Roberto G. Massolini; Giovanni Cesura; Rinaldo Castello (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A 0.23mm2 free coil ZigBee receiver based on a bond-wire self-oscillating mixer. - Marika Tedeschi; Antonio Liscidini; Rinaldo Castello (ESSCIRC, 2008)

A 2.4 GHz 3.6mW 0.35mm2 Quadrature Front-End RX for ZigBee and WPAN Applications. - Antonio Liscidini; Marika Tedeschi; Rinaldo Castello (ISSCC, 2008)

Analysis and Design of Configurable LNAs in Feedback Common-Gate Topologies. - Antonio Liscidini; Giuseppe Martini; Daniele Mastantuono; Rinaldo Castello (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Reconfigurable Narrow-Band MB-OFDM UWB Receiver Architecture. - Danilo Manstretta; Nicola Laurenti; Rinaldo Castello (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Time to digital converter based on a 2-dimensions Vernier architecture. - Antonio Liscidini; Luca Vercesi; Rinaldo Castello (CICC, 2009)

A VDSL2 CPE AFE in 0.15µm CMOS with integrated line driver. - Giovanni Cesura; Alessandro Bosi; Francesco Rezzi; Rinaldo Castello; Jenkin Chan; SaiBun Wong; Chi Fan Yung; Ovidiu Carnu; Thomas Cho (ISSCC, 2009)

A 1.25mW 75dB-SFDR CT filter with in-band noise reduction. - Antonio Liscidini; Alberto Pirola; Rinaldo Castello (ISSCC, 2009)

3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL. - Luca Fanori; Antonio Liscidini; Rinaldo Castello (ISSCC, 2010)

Class-G headphone driver in 65nm CMOS technology. - Alex Lollio; Giacomino Bollati; Rinaldo Castello (ISSCC, 2010)

Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning. - Luca Fanori; Antonio Liscidini; Rinaldo Castello (IEEE J. Solid State Circuits, 2010)

A Class-G Headphone Amplifier in 65 nm CMOS Technology. - Alex Lollio; Giacomino Bollati; Rinaldo Castello (IEEE J. Solid State Circuits, 2010)

Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping. - Alberto Pirola; Antonio Liscidini; Rinaldo Castello (IEEE J. Solid State Circuits, 2010)

Low-Power Quadrature Receivers for ZigBee (IEEE 802.15.4) Applications. - Marika Tedeschi; Antonio Liscidini; Rinaldo Castello (IEEE J. Solid State Circuits, 2010)

Two-Dimensions Vernier Time-to-Digital Converter. - Luca Vercesi; Antonio Liscidini; Rinaldo Castello (IEEE J. Solid State Circuits, 2010)

A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC. - Marco Sosio; Antonio Liscidini; Rinaldo Castello; Fernando De Bernardinis (ESSCIRC, 2011)

Corrections to "Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping" [Sep 10 1770-1780]. - Alberto Pirola; Antonio Liscidini; Rinaldo Castello (IEEE J. Solid State Circuits, 2011)

A 40MHz-to-1GHz fully integrated multistandard silicon tuner in 80nm CMOS. - Jody Greenberg; Fernando De Bernardinis; Carlo Tinella; Antonio Milani; Johnny Pan; Paola Uggetti; Marco Sosio; Shaoan Dai; Sam Tang; Giovanni Cesura; Gabriele Gandolfi; Vittorio Colonna; et al. (ISSCC, 2012)

A 36mW/9mW power-scalable DCO in 55nm CMOS for GSM/WCDMA frequency synthesizers. - Antonio Liscidini; Luca Fanori; Pietro Andreani; Rinaldo Castello (ISSCC, 2012)

A Dither-Less All Digital PLL for Cellular Transmitters. - Luca Vercesi; Luca Fanori; Fernando De Bernardinis; Antonio Liscidini; Rinaldo Castello (IEEE J. Solid State Circuits, 2012)

A 2G/3G Cellular Analog Baseband Based on a Filtering ADC. - Marco Sosio; Antonio Liscidini; Rinaldo Castello (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A low out-of-band noise LTE transmitter with current-mode approach. - Nicola Codega; Antonio Liscidini; Rinaldo Castello (ESSCIRC, 2013)

An LTE transmitter using a class-A/B power mixer. - Paolo Rossi; Nicola Codega; Danilo Gerna; Antonio Liscidini; Daniele Ottini; Yong He; Alberto Pirola; Enrico Sacchi; Gregory Uehara; Chao Yang; Rinaldo Castello (ISSCC, 2013)

SAW-Less Analog Front-End Receivers for TDD and FDD. - Ivan Fabiano; Marco Sosio; Antonio Liscidini; Rinaldo Castello (IEEE J. Solid State Circuits, 2013)

A 40-MHz-to-1-GHz Fully Integrated Multistandard Silicon Tuner in 80-nm CMOS. - Jody Greenberg; Fernando De Bernardinis; Carlo Tinella; Antonio Milani; Johnny Pan; Paola Uggetti; Marco Sosio; Shaoan Dai; Samuel Er-Shen Tang; Giovanni Cesura; Gabriele Gandolfi; Vittorio Colonna; et al. (IEEE J. Solid State Circuits, 2013)

An Intuitive Current-Driven Passive Mixer Model Based on Switched-Capacitor Theory. - Marco Sosio; Antonio Liscidini; Rinaldo Castello (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A 195.6dBc/Hz peak FoM P-N class-B oscillator with transformer-based tail filtering. - Marco Garampazzi; Paulo M. Mendes 002; Nicola Codega; Danilo Manstretta; Rinaldo Castello (ESSCIRC, 2014)

A multi-band Rel9 WCDMA/HSDPA/TDD LTE and FDD LTE transceiver with envelope tracking. - Shahrzad Tadjpour; Paolo Rossi; Luca Romanò; Ramesh Chokkalingam; Hamid Firouzkouhi; Feng Shi; M. Leroux; Danilo Gerna; A. Venca; John Vasa; Bala Ramachandran; Brian Brunn; et al. (ESSCIRC, 2014)

A low power/noise emission LTE fully class A/B transmitter with a programmable output balun. - Elisa Girard; Nicola Codega; Rinaldo Castello (ICECS, 2014)

A Current-Mode, Low Out-of-Band Noise LTE Transmitter With a Class-A/B Power Mixer. - Nicola Codega; Paolo Rossi; Alberto Pirola; Antonio Liscidini; Rinaldo Castello (IEEE J. Solid State Circuits, 2014)

An Intuitive Analysis of Phase Noise Fundamental Limits Suitable for Benchmarking LC Oscillators. - Marco Garampazzi; Stefano Dal Toso; Antonio Liscidini; Danilo Manstretta; P. Mendez; Luca Romanò; Rinaldo Castello (IEEE J. Solid State Circuits, 2014)

A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers. - Antonio Liscidini; Luca Fanori; Pietro Andreani; Rinaldo Castello (IEEE J. Solid State Circuits, 2014)

A 1.7-2.1GHz +23dBm TX power compatible blocker tolerant FDD receiver with integrated duplexer in 28nm CMOS. - Matteo Ramella; Ivan Fabiano; Danilo Manstretta; Rinaldo Castello (A-SSCC, 2015)

A 2.4GHz low-power SAW-less receiver for SoC coexistence. - Matteo Ramella; Ivan Fabiano; Danilo Manstretta; Rinaldo Castello (A-SSCC, 2015)

Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering. - Marco Garampazzi; Paulo M. Mendes 002; Nicola Codega; Danilo Manstretta; Rinaldo Castello (IEEE J. Solid State Circuits, 2015)

Highly linear TIA for SAW-less FDD receivers. - Giacomo Pini; Danilo Manstretta; Rinaldo Castello (A-SSCC, 2016)

A 0.7-2 GHz auxiliary receiver with enhanced compression for SAW-less FDD. - Danilo Montanari; Danilo Manstretta; Rinaldo Castello; Gerardo Castellano (ESSCIRC, 2017)

A 30μW, 3.3dB NF CMOS LNA for wearable WSN applications. - Ehsan Kargaran; Danilo Manstretta; Rinaldo Castello (ISCAS, 2017)

A SAW-Less 2.4-GHz Receiver Front-End With 2.4-mA Battery Current for SoC Coexistence. - Matteo Ramella; Ivan Fabiano; Danilo Manstretta; Rinaldo Castello (IEEE J. Solid State Circuits, 2017)

A Sub-1V, 220 μW Receiver Frontend for Wearable Wireless Sensor Network Applications. - Ehsan Kargaran; Danilo Manstretta; Rinaldo Castello (ISCAS, 2018)

A Mixer-1st Auxiliary Receiver for Full-Duplex Self-Interference Cancellation. - D. Prevcdelli; Giacomo Pini; Danilo Manstretta; Rinaldo Castello (NGCAS, 2018)

A Sub-IV, 72 μW Stacked LNA-VCO for Wireless Sensor Network Applications. - Ehsan Kargaran; Danilo Manstretta; Rinaldo Castello (PRIME, 2018)

A TVWS receiver with balanced output self-calibrated IIP2 LNTA employing a low-noise current multiplier. - Arianna Coccia; Saheed Tijani; Danilo Manstretta; Rinaldo Castello (Integr., 2018)

An FDD Wireless Diversity Receiver With Transmitter Leakage Cancellation in Transmit and Receive Bands. - Daniele Montanari; Gerardo Castellano; Ehsan Kargaran; Giacomo Pini; Saheed Tijani; Davide De Caro; Antonio Giuseppe Maria Strollo; Danilo Manstretta; Rinaldo Castello (IEEE J. Solid State Circuits, 2018)

Analysis and Design of a 20-MHz Bandwidth, 50.5-dBm OOB-IIP3, and 5.4-mW TIA for SAW-Less Receivers. - Giacomo Pini; Danilo Manstretta; Rinaldo Castello (IEEE J. Solid State Circuits, 2018)

Design and Analysis of 2.4 GHz 30 µW CMOS LNAs for Wearable WSN Applications. - Ehsan Kargaran; Danilo Manstretta; Rinaldo Castello (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Sub-0.6V, 330 µW, 0.15 mm2 Receiver Front-End for Bluetooth Low Energy (BLE) in 22 nm FD-SOI with Zero External Components. - Ehsan Kargaran; Carl Bryant; Danilo Manstretta; Jon Strange; Rinaldo Castello (A-SSCC, 2019)

A Wideband Saw-Less Transmitter Operating in Closed-Loop With Embedded N-Path Filtering. - Arianna Coccia; Danilo Manstretta; Rinaldo Castello; Luca Fanori (CICC, 2019)

A 260-MHz RF Bandwidth Mixer-First Receiver With Third-Order Current-Mode Filtering TIA. - Giacomo Pini; Danilo Manstretta; Rinaldo Castello (ESSCIRC, 2019)

A 150-MHz TIA with un-Conventional OTA Stabilization Technique via Local Active Feed-Back. - Mohammadmehdi Deilam Salehi; Danilo Manstretta; Rinaldo Castello (PRIME, 2019)

A 1.5-2.8 GHz current-mode LNTA achieving >25 dBm IIP3 and +8 dBm P-1dB gain compression. - Ehsan Kargaran; Danilo Manstretta; Rinaldo Castello (Microelectron. J., 2019)

Analysis and Design of a 260-MHz RF Bandwidth +22-dBm OOB-IIP3 Mixer-First Receiver With Third-Order Current-Mode Filtering TIA. - Giacomo Pini; Danilo Manstretta; Rinaldo Castello (IEEE J. Solid State Circuits, 2020)

A 400-µW Low-IF IoT Receiver Front-End with Tunable Charge-Sharing Complex Filter. - Jin Jin; Jianhui Wu 001; Rinaldo Castello; Danilo Manstretta (ESSCIRC, 2021)

A 17 mW 33 dBm IB-OIP3 0.5-1.5 GHz Bandwidth TIA Based on an Inductor-Stabilized OTA. - Nimesh Nadishka Miral; Danilo Manstretta; Rinaldo Castello (ESSCIRC, 2021)

A 2nd Order Current-Mode Filter with 14dB Variable Gain and 650MHz to 1GHz Tuning-Range in 28nm CMOS. - Karan Sohal; Danilo Manstretta; Rinaldo Castello (ISCAS, 2021)

A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture. - Mohsen Javadi; Hossein Miar Naimi; Saheed Tijani; Danilo Manstretta; Rinaldo Castello (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Filtering Trans-Impedance Amplifiers: from mW of Power to GHz of Bandwidth. - Nimesh Nadishka Miral; Karan Sohal; Danilo Manstretta; Rinaldo Castello (CICC, 2022)

Reminiscing through 40 years of CMOS analog circuit design: from audio to GHz. - Rinaldo Castello (ESSCIRC, 2022)

A 58 GHz Bandwidth, and less than 1.8% THD, Mach-Zehnder Driver, in 28 nm CMOS Technology. - Nicola Cordioli; Danilo Manstretta; Rinaldo Castello (ESSCIRC, 2022)

An FDD Auxiliary Receiver with a Highly Linear Low Noise Amplifier. - Jin Jin; Simone Lecchi; Rinaldo Castello; Danilo Manstretta (ESSCIRC, 2022)

A 400-μW IoT Low-IF Voltage-Mode Receiver Front-End With Charge-Sharing Complex Filter. - Jin Jin; Jianhui Wu 001; Rinaldo Castello; Danilo Manstretta (IEEE J. Solid State Circuits, 2022)

An Interferer-Tolerant RX with Translational Positive Feedback for 5G NR Applications Achieving 3.4 dB NF and 18 dBm OOB IIP3. - Simone Lecchi; Danilo Manstretta; Rinaldo Castello (ESSCIRC, 2023)

A 36 GHz Bandwidth, High Linear, Low Power, Driver Modulator, in 28 nm CMOS Technology Based on Quantized-Analog Signal Processing. - Xhulio Selmani; Gurjeet Singh; Rinaldo Castello; Antonio Liscidini (ISCAS, 2023)

A Wide Bandwidth, Low Power, Linear Quantized-Analog VGA in 28 nm CMOS Technology and 1.2V Supply. - Gurjeet Singh; Xhulio Selmani; Rinaldo Castello; Antonio Liscidini (PRIME, 2023)