A Comprehensive Analysis of Hybrid Phase-Modulated Converter With Current-Doubler Rectifier and Comparison With Its Center-Tapped Counterpart. - Rinkle Jain; Ned Mohan; Rajapandian Ayyanar 001; Robbert M. Button (IEEE Trans. Ind. Electron., 2006)

A novel control technique to eliminate output-voltage-ripple in switched-capacitor DC-DC converters. - Loai G. Salem; Rinkle Jain (ISCAS, 2011)

Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS. - Rinkle Jain; Stephen T. Kim; Vaibhav A. Vaidya; James W. Tschanz; Krishnan Ravichandran; Vivek De (CICC, 2014)

A staircase conductance modulation scheme for input-current-shaping in switched-capacitor DC-DC converters. - Sally Safwat; Rinkle Jain; Dawson Kesling (ISCAS, 2014)

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. - Carlos Tokunaga; Joseph F. Ryan 002; Charles Augustine; Jaydeep P. Kulkarni; Yi-Chun Shih; Stephen T. Kim; Rinkle Jain; Keith A. Bowman; Arijit Raychowdhury; Muhammad M. Khellah; James W. Tschanz; Vivek De (ISSCC, 2014)

A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS. - Rinkle Jain; Bibiche M. Geuskens; Stephen T. Kim; Muhammad M. Khellah; Jaydeep Kulkarni; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2014)

8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. - Stephen T. Kim; Yi-Chun Shih; Kaushik Mazumdar; Rinkle Jain; Joseph F. Ryan 002; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (ISSCC, 2015)

Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS. - Rinkle Jain; Stephen T. Kim; Vaibhav A. Vaidya; Krishnan Ravichandran; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2015)

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. - Stephen T. Kim; Yi-Chun Shih; Kaushik Mazumdar; Rinkle Jain; Joseph F. Ryan 002; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (IEEE J. Solid State Circuits, 2016)

20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS. - Harish Kumar Krishnamurthy; Vaibhav A. Vaidya; Sheldon Weng; Krishnan Ravichandran; Pavan Kumar 001; Stephen T. Kim; Rinkle Jain; George E. Matthew; Jim Tschanz; Vivek De (ISSCC, 2017)

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. - Pascal Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (ISSCC, 2018)

A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS. - Harish Kumar Krishnamurthy; Vaibhav A. Vaidya; Pavan Kumar 001; Rinkle Jain; Sheldon Weng; Stephen T. Kim; George E. Matthew; Nachiket V. Desai; Xiaosen Liu; Krishnan Ravichandran; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2018)

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{ text{MIN}}$ Optimization. - Pascal Andreas Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (IEEE J. Solid State Circuits, 2019)

A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOS. - Hao Luo; Somnath Kundu; Chun C. Lee; Rinkle Jain; Sarah Shahraini; Eduardo Alban; Timo Huusari; Jason Mix; Nasser A. Kurd; Mohamed Abdel-moneum; Brent R. Carlton (CICC, 2021)

A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer. - Minxiang Gong; Hua Chen; Xin Zhang 025; Rinkle Jain; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2023)

A 2-Gb/s UWB Transceiver for Short-Range Reconfigurable FDD Wireless Networks. - Renzhi Liu; K. T. Asma Beevi; Richard Dorrance; Timothy F. Cox; Rinkle Jain; Tolga Acikalin; Zhen Zhou; Tae-Young Yang; Johanny Escobar-Pelaez; Shuhei Yamada; Kenneth P. Foust; Brent R. Carlton (IEEE J. Solid State Circuits, 2023)

28.6 An 87% Efficient 2V-Input, 200A Voltage Regulator Chiplet Enabling Vertical Power Delivery in Multi-kW Systems-on-Package. - Rinkle Jain; Shunjiang Xu; Rajiv Kaushal; Carlos Mariscal; Humberto Caballero; Tamir Salus; Christopher Schaef; Anup Deka; Aruna Payala; Keng Chen; Huong T. Do; Jonathan Douglas (ISSCC, 2024)