Construction of polyvalent error control codes for multilevel memories. - Stefano Gregori; Pietro Ferrari; Rino Micheloni; Guido Torelli (ICECS, 2000)

Program word-line voltage generator for multilevel flash memories. - Osama Khouri; Rino Micheloni; Andrea Sacco; Giovanni Campardo; Guido Torelli (ICECS, 2000)

High-speed low-power sense comparator for multilevel flash memories. - Andrea Pierin; Stefano Gregori; Osama Khouri; Rino Micheloni; Guido Torelli (ICECS, 2000)

Fast Voltage Regulator for Multilevel Flash Memories. - Osama Khouri; Rino Micheloni; Stefano Gregori; Guido Torelli (MTDT, 2000)

Hierarchical Sector Biasing Organization for Flash Memories. - Rino Micheloni; Matteo Zammattio; Giovanni Campardo; Osama Khouri; Guido Torelli (MTDT, 2000)

40-mm2 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory. - Giovanni Campardo; Rino Micheloni; Stefano Commodaro; Emilio Yero; Matteo Zammattio; Sabina Mognoni; Andrea Sacco; Massimiliano Picca; Alessandro Manstretta; Marco Scotti; Ilaria Motta; C. Golla; et al. (IEEE J. Solid State Circuits, 2000)

Stand-by low-power architecture in a 3 V-only 2-bit/cell 64-Mbit flash memory. - Rino Micheloni; Ilaria Motta; Osama Khouri; Guido Torelli (ICECS, 2001)

An Error Control Code Scheme for Multilevel Flash Memories. - Stefano Gregori; Guido Torelli; Osama Khouri; Rino Micheloni (MTDT, 2001)

Low Output Resistance Charge Pump for Flash Memory Programming. - Osama Khouri; Stefano Gregori; Dario Soltesz; Guido Torelli; Rino Micheloni (MTDT, 2001)

The flash memory read path: building blocks and critical aspects. - Rino Micheloni; Luca Crippa; Miriam Sangalli; Giovanni Campardo (Proc. IEEE, 2003)

High-voltage management in single-supply CHE NOR-type flash memories. - Ilaria Motta; Giancarlo Ragone; Osama Khouri; Guido Torelli; Rino Micheloni (Proc. IEEE, 2003)

High input range sense comparator for multilevel Flash memories. - Alessandro Cabrini; Rino Micheloni; Osama Khouri; Stefano Gregori; Guido Torelli (ISCAS (2), 2004)

A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput. - Rino Micheloni; R. Ravasio; Alessia Marelli; E. Alice; V. Altieri; A. Bovino; Luca Crippa; E. Di Martino; L. D'Onofrio; A. Gambardella; E. Grillea; G. Guerra; et al. (ISSCC, 2006)

3-D Data Storage, Power Delivery, and RF/Optical Transceiver - Case Studies of 3-D Integration From System Design Perspectives. - Tong Zhang 002; Rino Micheloni; Guoyan Zhang; Zhaoran Rena Huang; James Jian-Qiang Lu (Proc. IEEE, 2009)

Non-Volatile Memories for Removable Media. - Rino Micheloni; Massimiliano Picca; Stefano Amato; Helmut Schwalm; Michael Scheppler; Stefano Commodaro (Proc. IEEE, 2009)

SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives. - Lorenzo Zuolo; Cristian Zambelli; Rino Micheloni; Salvatore Galfano; Marco Indaco; Stefano Di Carlo; Paolo Prinetto; Piero Olivo; Davide Bertozzi (DATE, 2014)

Overclocking nand Flash Memory I/O Link in LDPC-Based SSDs. - Kai Zhao 005; Jiangpeng Li; Jun Ma 012; Rino Micheloni; Tong Zhang 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Design space exploration of latency and bandwidth in RRAM-based solid state drives. - Lorenzo Zuolo; Cristian Zambelli; Rino Micheloni; Stephen Bates; Piero Olivo (NVMTS, 2015)

SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives. - Lorenzo Zuolo; Cristian Zambelli; Rino Micheloni; Marco Indaco; Stefano Di Carlo; Paolo Prinetto; Davide Bertozzi; Piero Olivo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

3D Charge Trap NAND Flash Memories. - Luca Crippa; Rino Micheloni (3D Flash Memories, 2016)

Advanced Architectures for 3D NAND Flash Memories with Vertical Channel. - Luca Crippa; Rino Micheloni (3D Flash Memories, 2016)

3D Multi-chip Integration and Packaging Technology for NAND Flash Memories. - Herb Huang; Rino Micheloni (3D Flash Memories, 2016)

BCH and LDPC Error Correction Codes for NAND Flash Memories. - Alessia Marelli; Rino Micheloni (3D Flash Memories, 2016)

3D Stacked NAND Flash Memories. - Rino Micheloni; Luca Crippa (3D Flash Memories, 2016)

3D Floating Gate NAND Flash Memories. - Rino Micheloni; Luca Crippa (3D Flash Memories, 2016)

Architectural and Integration Options for 3D NAND Flash Memories. - Rino Micheloni; Luca Crippa; Cristian Zambelli; Piero Olivo (Comput., 2017)

Solid-State Drive (SSD): A Nonvolatile Storage System. - Rino Micheloni (Proc. IEEE, 2017)

Array Architectures for 3-D NAND Flash Memories. - Rino Micheloni; Seiichi Aritome; Luca Crippa (Proc. IEEE, 2017)

Solid-State Drives (SSDs) [Scanning the Issue]. - Rino Micheloni; Piero Olivo (Proc. IEEE, 2017)

Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance. - Lorenzo Zuolo; Cristian Zambelli; Rino Micheloni; Piero Olivo (Proc. IEEE, 2017)

Fast Decoding of Low Density Lattice Codes. - Shuiyin Liu; Yi Hong 001; Emanuele Viterbo; Alessia Marelli; Rino Micheloni (CoRR, 2018)

Coset Probability Based Majority-logic Decoding for Non-binary LDPC Codes. - Viduranga Bandara Wijekoon; Shuiyin Liu; Emanuele Viterbo; Yi Hong 001; Rino Micheloni; Alessia Marelli (ITW, 2019)

Enabling Computational Storage Through FPGA Neural Network Accelerator for Enterprise SSD. - Cristian Zambelli; Riccardo Bertaggia; Lorenzo Zuolo; Rino Micheloni; Piero Olivo (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives. - Lorenzo Zuolo; Cristian Zambelli; Alessia Marelli; Rino Micheloni; Piero Olivo (IEEE Trans. Emerg. Top. Comput., 2019)

Efficient Decoding of Low Density Lattice Codes. - Shuiyin Liu; Yi Hong 001; Emanuele Viterbo; Alessia Marelli; Rino Micheloni (IEEE Wirel. Commun. Lett., 2019)

A Novel Graph Expansion and a Decoding Algorithm for NB-LDPC Codes. - Viduranga Bandara Wijekoon; Emanuele Viterbo; Yi Hong 001; Rino Micheloni; Alessia Marelli (IEEE Trans. Commun., 2020)

Logarithmic Non-uniform Quantization for List Decoding of Polar Codes. - Mohammad Rowshan; Emanuele Viterbo; Rino Micheloni; Alessia Marelli (CCWC, 2021)

Insights into device and material origins and physical mechanisms behind cross temperature in 3D NAND. - Milan Pesic; Bastien Beltrando; Tommaso Rollo; Cristian Zambelli; Andrea Padovani; Rino Micheloni; Rita Maji; Lisa Enman; Mark Saly; Yang Ho Bae; Jung-Bae Kim; Dong Kil Yim; et al. (IRPS, 2023)

An HPC Pipeline for Calcium Quantification of Aortic Root From Contrast-Enhanced CCT Scans. - Giada Minghini; Armando Ugo Cavallo; Andrea Miola; Valentina Sisini; Enrico Calore; Francesca Fortini; Rino Micheloni; Paola Rizzo; Sebastiano Fabio Schifano; Francesco Vieceli Dalla Sega; Cristian Zambelli (IEEE Access, 2023)

Modeling 3D NAND Flash with Nonparametric Inference on Regression Coefficients for Reliable Solid-State Storage. - Michela Borghesi; Cristian Zambelli; Rino Micheloni; Stefano Bonnini (Future Internet, 2023)

Leveraging Large-Scale TLC 3D NAND Flash Characterization to Investigate Early Lifetime Reliability of SSDs through Extreme Value Statistics. - Rino Micheloni; Luca Crippa; Alessia Marelli; Lorenzo Zuolo; Piero Olivo; Cristian Zambelli (IRPS, 2025)

High throughput edit distance computation on FPGA-based accelerators using HLS. - Sebastiano Fabio Schifano; Marco Reggiani; Enrico Calore; Rino Micheloni; Alessia Marelli; Cristian Zambelli (Future Gener. Comput. Syst., 2025)