Loop Scheduling for Transport Triggered Architecture Processors. - Perttu Salmela; Risto Mäkinen; Pekka Jääskeläinen; Jarmo Takala (SoC, 2006)

Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform. - Teemu Pitkänen; Risto Mäkinen; Jari Heikkinen; Tero Partanen; Jarmo Takala (SAMOS, 2006)

Parallel Memory Architecture for TTA Processor. - Jarno K. Tanskanen; Teemu Pitkänen; Risto Mäkinen; Jarmo Takala (SAMOS, 2007)

Parallel Memory Architecture for Application-Specific Instruction-Set Processors. - Teemu Pitkänen; Jarno K. Tanskanen; Risto Mäkinen; Jarmo Takala (J. Signal Process. Syst., 2009)