Area-efficient pipelining for FPGA-targeted high-level synthesis. - Ritchie Zhao; Mingxing Tan; Steve Dai; Zhiru Zhang (DAC, 2015)

ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests. - Mingxing Tan; Gai Liu; Ritchie Zhao; Steve Dai; Zhiru Zhang (ICCAD, 2015)

Improving high-level synthesis with decoupled data structure optimization. - Ritchie Zhao; Gai Liu; Shreesha Srinath; Christopher Batten; Zhiru Zhang (DAC, 2016)

Enabling adaptive loop pipelining in high-level synthesis. - Steve Dai; Gai Liu; Ritchie Zhao; Zhiru Zhang (ACSSC, 2017)

Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration. - Jeng-Hau Lin; Tianwei Xing; Ritchie Zhao; Zhiru Zhang; Mani B. Srivastava; Zhuowen Tu; Rajesh K. Gupta 001 (CVPR Workshops, 2017)

Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. - Steve Dai; Ritchie Zhao; Gai Liu; Shreesha Srinath; Udit Gupta; Christopher Batten; Zhiru Zhang (FPGA, 2017)

A Parallel Bandit-Based Approach for Autotuning FPGA Compilation. - Chang Xu 005; Gai Liu; Ritchie Zhao; Stephen Yang; Guojie Luo; Zhiru Zhang (FPGA, 2017)

Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs. - Ritchie Zhao; Weinan Song; Wentao Zhang; Tianwei Xing; Jeng-Hau Lin; Mani B. Srivastava; Rajesh Gupta 001; Zhiru Zhang (FPGA, 2017)

Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests. - Gai Liu; Mingxing Tan; Steve Dai; Ritchie Zhao; Zhiru Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. - Yuan Zhou; Udit Gupta; Steve Dai; Ritchie Zhao; Nitish Kumar Srivastava; Hanchen Jin; Joseph Featherston; Yi-Hsiang Lai; Gai Liu; Gustavo Angarita Velasquez; Wenping Wang; Zhiru Zhang (FPGA, 2018)

Serving DNNs in Real Time at Datacenter Scale with Project Brainwave. - Eric S. Chung; Jeremy Fowers; Kalin Ovtcharov; Michael Papamichael; Adrian M. Caulfield; Todd Massengill; Ming Liu; Daniel Lo; Shlomi Alkalay; Michael Haselman; Maleen Abeydeera; Logan Adams; et al. (IEEE Micro, 2018)

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. - Scott Davidson 004; Shaolin Xie; Christopher Torng; Khalid Al-Hawaj; Austin Rovinski; Tutu Ajayi; Luis Vega; Chun Zhao; Ritchie Zhao; Steve Dai; Aporva Amarnath; Bandhav Veluri; et al. (IEEE Micro, 2018)

Building Efficient Deep Neural Networks With Unitary Group Convolutions. - Ritchie Zhao; Yuwei Hu; Jordan Dotzel; Christopher De Sa; Zhiru Zhang (CVPR, 2019)

Improving Neural Network Quantization without Retraining using Outlier Channel Splitting. - Ritchie Zhao; Yuwei Hu; Jordan Dotzel; Christopher De Sa; Zhiru Zhang (ICML, 2019)

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. - Austin Rovinski; Chun Zhao; Khalid Al-Hawaj; Paul Gao 001; Shaolin Xie; Christopher Torng; Scott Davidson 004; Aporva Amarnath; Luis Vega; Bandhav Veluri; Anuj Rao; Tutu Ajayi; et al. (VLSI Circuits, 2019)

Overwrite Quantization: Opportunistic Outlier Handling for Neural Network Accelerators. - Ritchie Zhao; Christopher De Sa; Zhiru Zhang (CoRR, 2019)

Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. - Yichi Zhang 006; Ritchie Zhao; Weizhe Hua; Nayun Xu; G. Edward Suh; Zhiru Zhang (ICLR, 2020)

Pushing the Limits of Narrow Precision Inferencing at Cloud Scale with Microsoft Floating Point. - Bita Darvish Rouhani; Daniel Lo; Ritchie Zhao; Ming Liu; Jeremy Fowers; Kalin Ovtcharov; Anna Vinogradsky; Sarah Massengill; Lita Yang; Ray Bittner; Alessandro Forin; Haishan Zhu; et al. (NeurIPS, 2020)

With Shared Microexponents, A Little Shifting Goes a Long Way. - Bita Darvish Rouhani; Ritchie Zhao; Venmugil Elango; Rasoul Shafipour; Mathew Hall; Maral Mesmakhosroshahi; Ankit More; Levi Melnick; Maximilian Golub; Girish Varatkar; Lai Shao; Gaurav Kolhe; et al. (ISCA, 2023)

Shared Microexponents: A Little Shifting Goes a Long Way. - Bita Rouhani; Ritchie Zhao; Venmugil Elango; Rasoul Shafipour; Mathew Hall; Maral Mesmakhosroshahi; Ankit More; Levi Melnick; Maximilian Golub; Girish Varatkar; Lei Shao; Gaurav Kolhe; et al. (CoRR, 2023)

Microscaling Data Formats for Deep Learning. - Bita Darvish Rouhani; Ritchie Zhao; Ankit More; Mathew Hall; Alireza Khodamoradi; Summer Deng; Dhruv Choudhary; Marius Cornea; Eric Dellinger; Kristof Denolf; Dusan Stosic; Venmugil Elango; et al. (CoRR, 2023)

ResMoE: Space-efficient Compression of Mixture of Experts LLMs via Residual Restoration. - Mengting Ai; Tianxin Wei; Yifan Chen 004; Zhichen Zeng 001; Ritchie Zhao; Girish Varatkar; Bita Darvish Rouhani; Xianfeng Tang; Hanghang Tong; Jingrui He (KDD (1), 2025)

Post-Training Quantization for 3D Medical Image Segmentation: A Practical Study on Real Inference Engines. - Chongyu Qu; Ritchie Zhao; Ye Yu; Bin Liu; Tianyuan Yao; Junchao Zhu; Bennett A. Landman; Yucheng Tang; Yuankai Huo (CoRR, 2025)

RocketKV: Accelerating Long-Context LLM Inference via Two-Stage KV Cache Compression. - Payman Behnam; Yaosheng Fu; Ritchie Zhao; Po-An Tsai; Zhiding Yu; Alexey Tumanov (CoRR, 2025)

Beyond the Buzz: A Pragmatic Take on Inference Disaggregation. - Tiyasa Mitra; Ritika Borkar; Nidhi Bhatia; Ramon Matas; Shivam Raj; Dheevatsa Mudigere; Ritchie Zhao; Maximilian Golub; Arpan Dutta; Sailaja Madduri; Dharmesh Jani; Brian Pharris; et al. (CoRR, 2025)

Helix Parallelism: Rethinking Sharding Strategies for Interactive Multi-Million-Token LLM Decoding. - Nidhi Bhatia; Ankit More; Ritika Borkar; Tiyasa Mitra; Ramon Matas; Ritchie Zhao; Maximilian Golub; Dheevatsa Mudigere; Brian Pharris; Bita Darvish Rouhani (CoRR, 2025)

EMPIRIC: Exploring Missing Pieces in KV Cache Compression for Reducing Computation, Storage, and Latency in Long-Context LLM Inference. - Payman Behnam; Yaosheng Fu; Ritchie Zhao; Po-An Tsai; Zhiding Yu; Alexey Tumanov (ACM SIGOPS Oper. Syst. Rev., 2025)