Design Tradeoffs and Predistortion of Digital Cartesian RF-Power-DAC Transmitters. - Ritesh Bhat; Harish Krishnaswamy (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

13.10 A >1W 2.2GHz switched-capacitor digital power amplifier with wideband mixed-domain multi-tap FIR filtering of OOB noise floor. - Ritesh Bhat; Jin Zhou 001; Harish Krishnaswamy (ISSCC, 2017)

Wideband Mixed-Domain Multi-Tap Finite-Impulse Response Filtering of Out-of-Band Noise Floor in Watt-Class Digital Transmitters. - Ritesh Bhat; Jin Zhou 001; Harish Krishnaswamy (IEEE J. Solid State Circuits, 2017)

Revolutionizing Aerospace and Defense: The Impact of AI and Robotics on Modern Warfare. - Dasharathraj K. Shetty; Gayathri Prerepa; Nithesh Naik; Ritesh Bhat; Jayant Sharma 003; Parva Mehrotra (ICIMMI, 2022)

A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology. - Steven Callender; Amy Whitcombe; Abhishek Agrawal; Ritesh Bhat; Mustafijur Rahman; Chun C. Lee; Peter Sagazio; Georgios C. Dogiamis; Brent R. Carlton; Mark Chakravorti; Stefano Pellerano; Christopher D. Hull (ISSCC, 2022)

A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET. - Steven Callender; Abhishek Agrawal; Amy Whitcombe; Ritesh Bhat; Mustafijur Rahman; Chun C. Lee; Peter Sagazio; Georgios C. Dogiamis; Brent R. Carlton; Christopher D. Hull; Stefano Pellerano (IEEE J. Solid State Circuits, 2022)

A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET. - Abhishek Agrawal; Amy Whitcombe; Woorim Shin; Ritesh Bhat; Somnath Kundu; Peter Sagazio; Hariprasad Chandrakumar; Thomas William Brown; Brent R. Carlton; Christopher D. Hull; Steven Callender; Stefano Pellerano (ISSCC, 2023)

A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET. - Abhishek Agrawal; Amy Whitcombe; Woorim Shin; Ritesh Bhat; Somnath Kundu; Peter Sagazio; Hariprasad Chandrakumar; Thomas William Brown; Brent R. Carlton; Christopher Dennis Hull; Steven Callender; Stefano Pellerano (IEEE J. Solid State Circuits, 2023)