Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. - Ritesh Rajore; Ganesh Garga; H. S. Jamadagni; S. K. Nandy 001 (ASAP, 2008)

Architecture of Run-Time Reconfigurable Channel Decoder. - Ritesh Rajore; S. K. Nandy 001; H. S. Jamadagni (ICC, 2009)